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turnip: Use the util cache helpers

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37803>
This commit is contained in:
Faith Ekstrand 2025-07-24 20:15:18 +00:00 • committed by Marge Bot
parent 1fbc73836e
commit 72c9256d8f
3 changed files with 8 additions and 66 deletions
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3
src/freedreno/vulkan/tu_device.cc
View file

@ -15,6 +15,7 @@
#include <poll.h>
#include "git_sha1.h"
#include "util/cache_ops.h"
#include "util/u_debug.h"
#include "util/disk_cache.h"
#include "util/hex.h"
@ -1607,7 +1608,7 @@ tu_physical_device_init(struct tu_physical_device *device,
goto fail_free_name;
}
device->level1_dcache_size = tu_get_l1_dcache_size();
device->level1_dcache_size = util_cache_granularity();
device->has_cached_non_coherent_memory =
device->level1_dcache_size > 0 && !DETECT_ARCH_ARM;

69
src/freedreno/vulkan/tu_knl.cc
View file

@ -20,6 +20,7 @@
#include "vk_debug_utils.h"
#include "util/cache_ops.h"
#include "util/libdrm.h"
#include "tu_device.h"
@ -139,40 +140,6 @@ tu_bo_unmap(struct tu_device *dev, struct tu_bo *bo, bool reserve)
return VK_SUCCESS;
}
static inline void
tu_sync_cacheline_to_gpu(void const *p __attribute__((unused)))
{
#if DETECT_ARCH_AARCH64
/* Clean data cache. */
__asm volatile("dc cvac, %0" : : "r" (p) : "memory");
#elif (DETECT_ARCH_X86 || DETECT_ARCH_X86_64)
__builtin_ia32_clflush(p);
#elif DETECT_ARCH_ARM
/* DCCMVAC - same as DC CVAC on aarch64.
* Seems to be illegal to call from userspace.
*/
//__asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r" (p) : "memory");
UNREACHABLE("Cache line clean is unsupported on ARMv7");
#endif
}
static inline void
tu_sync_cacheline_from_gpu(void const *p __attribute__((unused)))
{
#if DETECT_ARCH_AARCH64
/* Clean and Invalidate data cache, there is no separate Invalidate. */
__asm volatile("dc civac, %0" : : "r" (p) : "memory");
#elif (DETECT_ARCH_X86 || DETECT_ARCH_X86_64)
__builtin_ia32_clflush(p);
#elif DETECT_ARCH_ARM
/* DCCIMVAC - same as DC CIVAC on aarch64.
* Seems to be illegal to call from userspace.
*/
//__asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (p) : "memory");
UNREACHABLE("Cache line invalidate is unsupported on ARMv7");
#endif
}
void
tu_bo_sync_cache(struct tu_device *dev,
struct tu_bo *bo,
@ -180,40 +147,16 @@ tu_bo_sync_cache(struct tu_device *dev,
VkDeviceSize size,
enum tu_mem_sync_op op)
{
uintptr_t level1_dcache_size = dev->physical_device->level1_dcache_size;
char *start = (char *) bo->map + offset;
char *end = start + (size == VK_WHOLE_SIZE ? (bo->size - offset) : size);
start = (char *) ((uintptr_t) start & ~(level1_dcache_size - 1));
for (; start < end; start += level1_dcache_size) {
if (op == TU_MEM_SYNC_CACHE_TO_GPU) {
tu_sync_cacheline_to_gpu(start);
} else {
tu_sync_cacheline_from_gpu(start);
}
size = size == VK_WHOLE_SIZE ? (bo->size - offset) : size;
if (op == TU_MEM_SYNC_CACHE_TO_GPU) {
util_flush_range(start, size);
} else {
util_flush_inval_range(start, size);
}
}
uint32_t
tu_get_l1_dcache_size()
{
if (!(DETECT_ARCH_AARCH64 || DETECT_ARCH_X86 || DETECT_ARCH_X86_64))
return 0;
#if DETECT_ARCH_AARCH64 && \
(!defined(_SC_LEVEL1_DCACHE_LINESIZE) || DETECT_OS_ANDROID)
/* Bionic does not implement _SC_LEVEL1_DCACHE_LINESIZE properly: */
uint64_t ctr_el0;
asm("mrs\t%x0, ctr_el0" : "=r"(ctr_el0));
return 4 << ((ctr_el0 >> 16) & 0xf);
#elif defined(_SC_LEVEL1_DCACHE_LINESIZE)
return sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
#else
return 0;
#endif
}
void tu_bo_allow_dump(struct tu_device *dev, struct tu_bo *bo)
{
dev->instance->knl->bo_allow_dump(dev, bo);

2
src/freedreno/vulkan/tu_knl.h
View file

@ -224,8 +224,6 @@ tu_bo_sync_cache(struct tu_device *dev,
VkDeviceSize size,
enum tu_mem_sync_op op);
uint32_t tu_get_l1_dcache_size();
void tu_bo_allow_dump(struct tu_device *dev, struct tu_bo *bo);
void tu_bo_set_metadata(struct tu_device *dev, struct tu_bo *bo,