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i965: always set tiling for fbo depth buffer on sandybridge

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Sandybridge requires depth buffer must be tiling.

Fix 'fbo_firecube' demo.
This commit is contained in:
Zhenyu Wang 2010-09-30 10:49:47 +08:00
parent 83278d384e
commit 72b368ae69
1 changed files with 8 additions and 2 deletions
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10
src/mesa/drivers/dri/intel/intel_fbo.c
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@ -102,7 +102,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
{
struct intel_context *intel = intel_context(ctx);
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
int cpp;
int cpp, tiling;
ASSERT(rb->Name != 0);
@ -176,7 +176,13 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
/* alloc hardware renderbuffer */
DBG("Allocating %d x %d Intel RBO\n", width, height);
irb->region = intel_region_alloc(intel->intelScreen, I915_TILING_NONE, cpp,
tiling = I915_TILING_NONE;
/* Gen6 requires depth must be tiling */
if (intel->gen >= 6 && rb->Format == MESA_FORMAT_S8_Z24)
tiling = I915_TILING_Y;
irb->region = intel_region_alloc(intel->intelScreen, tiling, cpp,
width, height, GL_TRUE);
if (!irb->region)
return GL_FALSE; /* out of memory? */