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winsys/amdgpu: Enlarge const IB size.

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Necessary to prevent performance regressions due to extra flushing.

Probably should enlarge it even further when also updating
uniforms through the CE, but this seems large enough for now.

v2: Add preamble IB.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Bas Nieuwenhuizen 2016-04-14 02:11:07 +02:00
parent 7997b5f005
commit 7201230582
1 changed files with 20 additions and 8 deletions
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28
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
View file

@ -199,14 +199,26 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx)
/* COMMAND SUBMISSION */
static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_ib *ib,
struct amdgpu_cs_ib_info *info)
struct amdgpu_cs_ib_info *info, unsigned ib_type)
{
/* Small IBs are better than big IBs, because the GPU goes idle quicker
* and there is less waiting for buffers and fences. Proof:
* http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
*/
const unsigned buffer_size = 128 * 1024 * 4;
const unsigned ib_size = 20 * 1024 * 4;
unsigned buffer_size, ib_size;
switch (ib_type) {
case IB_CONST_PREAMBLE:
buffer_size = 4 * 1024 * 4;
ib_size = 1024 * 4;
case IB_CONST:
buffer_size = 512 * 1024 * 4;
ib_size = 128 * 1024 * 4;
break;
case IB_MAIN:
buffer_size = 128 * 1024 * 4;
ib_size = 20 * 1024 * 4;
}
ib->base.cdw = 0;
ib->base.buf = NULL;
@ -350,7 +362,7 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
return NULL;
}
if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN])) {
if (!amdgpu_get_new_ib(&ctx->ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN)) {
amdgpu_destroy_cs_context(cs);
FREE(cs);
return NULL;
@ -373,7 +385,7 @@ amdgpu_cs_add_const_ib(struct radeon_winsys_cs *rcs)
if (cs->ring_type != RING_GFX || cs->const_ib.ib_mapped)
return NULL;
if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST]))
if (!amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST))
return NULL;
cs->request.number_of_ibs = 2;
@ -760,12 +772,12 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
cleanup:
amdgpu_cs_context_cleanup(cs);
amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN]);
amdgpu_get_new_ib(&ws->base, &cs->main, &cs->ib[IB_MAIN], IB_MAIN);
if (cs->const_ib.ib_mapped)
amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST]);
amdgpu_get_new_ib(&ws->base, &cs->const_ib, &cs->ib[IB_CONST], IB_CONST);
if (cs->const_preamble_ib.ib_mapped)
amdgpu_get_new_ib(&ws->base, &cs->const_preamble_ib,
&cs->ib[IB_CONST_PREAMBLE]);
&cs->ib[IB_CONST_PREAMBLE], IB_CONST_PREAMBLE);
ws->num_cs_flushes++;
}