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freedreno/afuc: Emulate THREAD_SYNC on a660

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This is similar to a7xx but slightly different, because it inverts the
sense of the bits (the firmware sets to 1 once it starts) and there are
only 2 processors. We didn't need this before because the waiting on
THREAD_SYNC only happens after setting the packet table.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26771>
This commit is contained in:
Connor Abbott 2023-12-19 19:37:51 -05:00 • committed by Marge Bot
parent 7e9380e2bc
commit 71f80d3deb
4 changed files with 20 additions and 0 deletions
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11
src/freedreno/afuc/emu-regs.c
View file

@ -160,11 +160,22 @@ emu_get_gpu_reg(struct emu *emu, unsigned n)
void
emu_set_gpu_reg(struct emu *emu, unsigned n, uint32_t val)
{
EMU_GPU_REG(CP_LPAC_SQE_CNTL);
EMU_CONTROL_REG(THREAD_SYNC);
if (n >= ARRAY_SIZE(emu->gpu_regs.val))
return;
assert(n < ARRAY_SIZE(emu->gpu_regs.val));
BITSET_SET(emu->gpu_regs.written, n);
emu->gpu_regs.val[n] = val;
if (n == emu_reg_offset(&CP_LPAC_SQE_CNTL)) {
/* This is sort-of a hack, but emulate what the LPAC bootstrap routine
* does so that the main bootstrap routine doesn't get stuck.
*/
emu_set_reg32(emu, &THREAD_SYNC,
emu_get_reg32(emu, &THREAD_SYNC) | (1u << 1));
}
}
static bool

6
src/freedreno/afuc/emu.c
View file

@ -461,10 +461,16 @@ void
emu_run_bootstrap(struct emu *emu)
{
EMU_CONTROL_REG(PACKET_TABLE_WRITE_ADDR);
EMU_CONTROL_REG(THREAD_SYNC);
emu->quiet = true;
emu->run_mode = true;
if (gpuver == 6 && emu->processor == EMU_PROC_LPAC) {
/* Emulate what the SQE bootstrap routine does after launching LPAC */
emu_set_reg32(emu, &THREAD_SYNC, 1u << 0);
}
while (emu_get_reg32(emu, &PACKET_TABLE_WRITE_ADDR) < 0x80) {
emu_step(emu);
}

1
src/freedreno/registers/adreno/a6xx.xml
View file

@ -1458,6 +1458,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
<reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>
<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>

2
src/freedreno/registers/adreno/adreno_control_regs.xml
View file

@ -271,6 +271,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<!-- new in gen3+ -->
<reg32 name="PRED_REG" offset="0x17f"/>
<reg32 name="THREAD_SYNC" offset="0x200"/>
</domain>
<domain name="A7XX_CONTROL_REG" width="32">