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anv: add an option to disable push constant space reallocation
Already called in genX(batch_emit_push_constants_alloc) above. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39584>
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a21da01994
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718a5d48b8
6 changed files with 28 additions and 23 deletions
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@ -34,6 +34,7 @@ static const driOptionDescription anv_dri_options[] = {
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DRI_CONF_NO_16BIT(false)
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DRI_CONF_INTEL_BINDING_TABLE_BLOCK_SIZE(BINDING_TABLE_POOL_DEFAULT_BLOCK_SIZE,
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1024, 128 * 1024)
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DRI_CONF_INTEL_DISABLE_PUSH_CONSTANT_ALLOC(true)
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DRI_CONF_INTEL_ENABLE_WA_14018912822(false)
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DRI_CONF_INTEL_ENABLE_WA_14024015672_MSAA(false)
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DRI_CONF_INTEL_SAMPLER_ROUTE_TO_LSC(false)
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@ -292,6 +293,8 @@ anv_init_dri_options(struct anv_instance *instance)
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driQueryOptionb(&instance->dri_options, "anv_barrier_post_typed_clear_shader");
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instance->barrier_post_untyped_clear_shader =
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driQueryOptionb(&instance->dri_options, "anv_barrier_post_untyped_clear_shader");
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instance->disable_push_constant_alloc =
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driQueryOptionb(&instance->dri_options, "intel_disable_push_constant_alloc");
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if (instance->vk.app_info.engine_name &&
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!strcmp(instance->vk.app_info.engine_name, "DXVK")) {
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@ -1785,6 +1785,7 @@ struct anv_instance {
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*/
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unsigned binding_table_block_size;
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bool disable_lto;
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bool disable_push_constant_alloc;
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enum brw_divergent_atomics_flags enable_opt_divergent_atomics;
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bool force_sampler_prefetch;
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bool force_compute_surface_prefetch;
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@ -42,8 +42,8 @@ batch_emit_push_constants_alloc(struct anv_batch *batch,
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VkShaderStageFlags stages)
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{
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const unsigned push_constant_kb =
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(stages & VK_SHADER_STAGE_MESH_BIT_EXT) ?
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device->info->mesh_max_constant_urb_size_kb :
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/* GFX_VERx10 >= 125 ? */
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/* devinfo->mesh_max_constant_urb_size_kb : */
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device->info->max_constant_urb_size_kb;
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/* On Gfx12.5 there is no more push constant allocation required */
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@ -107,10 +107,12 @@ genX(batch_emit_push_constants_alloc)(struct anv_batch *batch,
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static void
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cmd_buffer_alloc_gfx_push_constants(struct anv_cmd_buffer *cmd_buffer)
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{
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if (cmd_buffer->device->physical->instance->disable_push_constant_alloc)
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return;
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struct anv_cmd_graphics_state *gfx = &cmd_buffer->state.gfx;
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const VkShaderStageFlags stages =
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genX(push_constant_alloc_stages)(gfx->active_stages);
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if (stages == cmd_buffer->state.gfx.push_constant_stages)
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return;
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@ -783,6 +783,16 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
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}
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#endif
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if (device->physical->instance->disable_push_constant_alloc) {
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genX(batch_emit_push_constants_alloc)(
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batch, device,
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VK_SHADER_STAGE_VERTEX_BIT |
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VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT |
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VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT |
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VK_SHADER_STAGE_GEOMETRY_BIT |
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VK_SHADER_STAGE_FRAGMENT_BIT);
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}
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anv_batch_emit(batch, GENX(MI_BATCH_BUFFER_END), bbe);
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result = batch->status;
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@ -273,27 +273,12 @@ genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state)
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anv_batch_emit(batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);
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#endif
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VkShaderStageFlags push_stages =
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genX(push_constant_alloc_stages)(VK_SHADER_STAGE_FRAGMENT_BIT);
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genX(batch_emit_push_constants_alloc)(batch, device, push_stages);
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state->cmd_buffer->state.gfx.push_constant_stages = push_stages;
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#if GFX_VERx10 == 125
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/* DG2: Wa_22011440098
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* MTL: Wa_18022330953
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*
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* In 3D mode, after programming push constant alloc command immediately
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* program push constant command(ZERO length) without any commit between
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* them.
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*
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* Note that Wa_16011448509 isn't needed here as all address bits are zero.
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*/
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anv_batch_emit(batch, GENX(3DSTATE_CONSTANT_ALL), c) {
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/* Update empty push constants for all stages (bitmask = 11111b) */
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c.ShaderUpdateEnable = 0x1f;
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c.MOCS = anv_mocs(device, NULL, 0);
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if (!device->physical->instance->disable_push_constant_alloc) {
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VkShaderStageFlags push_stages =
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genX(push_constant_alloc_stages)(VK_SHADER_STAGE_FRAGMENT_BIT);
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genX(batch_emit_push_constants_alloc)(batch, device, push_stages);
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state->cmd_buffer->state.gfx.push_constant_stages = push_stages;
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}
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#endif
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#if GFX_VER == 9
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/* Allocate a binding table for Gfx9 because the HW does not have a null-rt
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@ -361,6 +361,10 @@
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DRI_CONF_OPT_I(intel_binding_table_block_size, def, min, max, \
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"Intel binding table block allocation size (3DSTATE_BINDING_TABLE_POOL_ALLOC)")
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#define DRI_CONF_INTEL_DISABLE_PUSH_CONSTANT_ALLOC(def) \
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DRI_CONF_OPT_B(intel_disable_push_constant_alloc, def, \
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"Disable push constant space allocations")
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#define DRI_CONFIG_INTEL_TBIMR(def) \
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DRI_CONF_OPT_B(intel_tbimr, def, "Enable TBIMR tiled rendering")
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