From 7108619c0d6afaf4331088b7792a3a313db9c745 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 25 Nov 2022 19:46:15 -0500 Subject: [PATCH] agx: Handle 32-bit gl_FragCoord.zw The coefficient register is 16-bit so our builder will make the iter 16-bit too (maybe not the best design...), force fp32 to match the NIR intrinsic. Fixes glsl-fs-fragcoord-zw-ortho Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/compiler/agx_compile.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index a7f062c1987..e841313a1c2 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -682,8 +682,9 @@ agx_emit_load_frag_coord(agx_builder *b, agx_index dst, nir_intrinsic_instr *ins agx_index dests[4] = { agx_null() }; u_foreach_bit(i, nir_ssa_def_components_read(&instr->dest.ssa)) { + agx_index fp32 = agx_temp(b->shader, AGX_SIZE_32); + if (i < 2) { - agx_index fp32 = agx_temp(b->shader, AGX_SIZE_32); agx_convert_to(b, fp32, agx_immediate(AGX_CONVERT_U32_TO_F), agx_get_sr(b, 32, AGX_SR_THREAD_POSITION_IN_GRID_X + i), AGX_ROUND_RTE); @@ -691,7 +692,9 @@ agx_emit_load_frag_coord(agx_builder *b, agx_index dst, nir_intrinsic_instr *ins dests[i] = agx_fadd(b, fp32, agx_immediate_f(0.5f)); } else { agx_index cf = agx_get_cf(b->shader, true, false, VARYING_SLOT_POS, i, 1); - dests[i] = agx_iter(b, cf, agx_null(), 1, false); + + dests[i] = fp32; + agx_iter_to(b, fp32, cf, agx_null(), 1, false); } }