From 707c53d5349ba44e83f98dca043aa56809f6e2b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 2 Mar 2026 17:20:23 -0500 Subject: [PATCH] ac: replace some packet field definitions in sid.h by generated ones --- src/amd/common/ac_cmdbuf_cp.c | 4 +- src/amd/common/ac_shadowed_regs.c | 22 +++---- src/amd/common/ac_sqtt.c | 2 +- src/amd/common/sid.h | 62 ++++--------------- src/amd/vulkan/radv_cmd_buffer.c | 6 +- src/amd/vulkan/radv_dgc.c | 8 +-- src/amd/vulkan/radv_queue.c | 6 +- .../drivers/radeonsi/si_cp_reg_shadowing.c | 14 ++--- src/gallium/drivers/radeonsi/si_query.c | 8 +-- src/gallium/drivers/radeonsi/si_sqtt.c | 8 +-- src/gallium/drivers/radeonsi/si_state.c | 36 +++++------ .../drivers/radeonsi/si_state_draw.cpp | 4 +- src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp | 10 +-- src/gallium/winsys/amdgpu/drm/amdgpu_userq.c | 4 +- 14 files changed, 78 insertions(+), 116 deletions(-) diff --git a/src/amd/common/ac_cmdbuf_cp.c b/src/amd/common/ac_cmdbuf_cp.c index 4ba512b7952..a4a9340085d 100644 --- a/src/amd/common/ac_cmdbuf_cp.c +++ b/src/amd/common/ac_cmdbuf_cp.c @@ -538,8 +538,8 @@ ac_emit_cp_atomic_mem(struct ac_cmdbuf *cs, uint32_t atomic_op, { ac_cmdbuf_begin(cs); ac_cmdbuf_emit(PKT3(PKT3_ATOMIC_MEM, 7, 0)); - ac_cmdbuf_emit(ATOMIC_OP(atomic_op) | - ATOMIC_COMMAND(atomic_cmd)); + ac_cmdbuf_emit(S_1E_1_ATOMIC(atomic_op) | + S_1E_1_COMMAND(atomic_cmd)); ac_cmdbuf_emit(va); /* addr lo */ ac_cmdbuf_emit(va >> 32); /* addr hi */ ac_cmdbuf_emit(data); /* data lo */ diff --git a/src/amd/common/ac_shadowed_regs.c b/src/amd/common/ac_shadowed_regs.c index 435b497e965..a94ff4e8834 100644 --- a/src/amd/common/ac_shadowed_regs.c +++ b/src/amd/common/ac_shadowed_regs.c @@ -3069,18 +3069,18 @@ struct ac_pm4_state *ac_create_shadowing_ib_preamble(const struct radeon_info *i ac_pm4_cmd_add(pm4, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); ac_pm4_cmd_add(pm4, - CC0_UPDATE_LOAD_ENABLES(1) | - CC0_LOAD_PER_CONTEXT_STATE(1) | - CC0_LOAD_CS_SH_REGS(1) | - CC0_LOAD_GFX_SH_REGS(1) | - CC0_LOAD_GLOBAL_UCONFIG(1)); + S_28_1_UPDATE_LOAD_ENABLES(1) | + S_28_1_LOAD_PER_CONTEXT_STATE(1) | + S_28_1_LOAD_CS_SH_REGS(1) | + S_28_1_LOAD_GFX_SH_REGS(1) | + S_28_1_LOAD_GLOBAL_UCONFIG(1)); ac_pm4_cmd_add(pm4, - CC1_UPDATE_SHADOW_ENABLES(1) | - CC1_SHADOW_PER_CONTEXT_STATE(1) | - CC1_SHADOW_CS_SH_REGS(1) | - CC1_SHADOW_GFX_SH_REGS(1) | - CC1_SHADOW_GLOBAL_UCONFIG(1) | - CC1_SHADOW_GLOBAL_CONFIG(1)); + S_28_2_UPDATE_SHADOW_ENABLES(1) | + S_28_2_SHADOW_PER_CONTEXT_STATE(1) | + S_28_2_SHADOW_CS_SH_REGS(1) | + S_28_2_SHADOW_GFX_SH_REGS(1) | + S_28_2_SHADOW_GLOBAL_UCONFIG(1) | + S_28_2_SHADOW_GLOBAL_CONFIG(1)); for (unsigned i = 0; i < SI_NUM_REG_RANGES; i++) ac_build_load_reg(info, pm4, i, gpu_address); diff --git a/src/amd/common/ac_sqtt.c b/src/amd/common/ac_sqtt.c index 02bea38f819..f3d4130087c 100644 --- a/src/amd/common/ac_sqtt.c +++ b/src/amd/common/ac_sqtt.c @@ -594,7 +594,7 @@ ac_sqtt_copy_info_regs(const struct radeon_info *info, struct ac_pm4_state *pm4, uint32_t init_wptr_value = shifted_data_va & 0x1fffffff; ac_pm4_cmd_add(pm4, PKT3(PKT3_ATOMIC_MEM, 7, 0)); - ac_pm4_cmd_add(pm4, ATOMIC_OP(TC_OP_ATOMIC_SUB_RTN_32)); + ac_pm4_cmd_add(pm4, S_1E_1_ATOMIC(V_1E_1_GL2_OP_ATOMIC_SUB_RTN_32)); ac_pm4_cmd_add(pm4, info_va); /* addr lo */ ac_pm4_cmd_add(pm4, info_va >> 32); /* addr hi */ ac_pm4_cmd_add(pm4, init_wptr_value); /* data lo */ diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index c5fab6d1761..73bf0c49925 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -36,10 +36,6 @@ #define SI_SHADOWED_REG_BUFFER_SIZE \ (SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE + SI_UCONFIG_REG_SPACE_SIZE) -/* All registers defined in this packet section don't exist and the only - * purpose of these definitions is to define packet encoding that - * the IB parser understands, and also to have an accurate documentation. - */ #define PKT3_NOP 0x10 #define PKT3_SET_BASE 0x11 #define PKT3_CLEAR_STATE 0x12 @@ -47,58 +43,27 @@ #define PKT3_DISPATCH_DIRECT 0x15 #define PKT3_DISPATCH_INDIRECT 0x16 #define PKT3_ATOMIC_MEM 0x1E -#define ATOMIC_OP(x) ((unsigned)((x)&0x7f) << 0) -#define TC_OP_ATOMIC_SUB_RTN_32 16 -#define TC_OP_ATOMIC_SUB_RTN_64 48 -#define TC_OP_ATOMIC_CMPSWAP_32 72 -#define TC_OP_ATOMIC_SUB_64 112 -#define TC_OP_ATOMIC_XOR_64 119 -#define ATOMIC_COMMAND(x) ((unsigned)((x)&0x3) << 8) -#define ATOMIC_COMMAND_SEND_RTN 0x0 /* only RTN opcodes */ -#define ATOMIC_COMMAND_LOOP 0x1 /* only RTN opcodes */ -#define ATOMIC_COMMAND_WR_CONFIRM 0x2 /* only non-RTN opcodes */ -#define ATOMIC_COMMAND_SEND_NO_RTN 0x3 /* only non-RTN opcodes */ -#define ATOMIC_ENGINE_PFP (1 << 30) #define PKT3_OCCLUSION_QUERY 0x1F /* GFX7+ */ #define PKT3_SET_PREDICATION 0x20 -#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) -#define PREDICATION_DRAW_VISIBLE (1 << 8) -#define PREDICATION_HINT_WAIT (0 << 12) -#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) -#define PRED_OP(x) ((x) << 16) -#define PREDICATION_OP_CLEAR 0x0 -#define PREDICATION_OP_ZPASS 0x1 -#define PREDICATION_OP_PRIMCOUNT 0x2 -#define PREDICATION_OP_BOOL64 0x3 -#define PREDICATION_OP_BOOL32 0x4 -#define PREDICATION_CONTINUE (1 << 31) +#define PREDICATION_DRAW_NOT_VISIBLE S_20_1_PRED_BOOL(V_20_1_DRAW_IF_NOT_VISIBLE_OR_OVERFLOW) +#define PREDICATION_DRAW_VISIBLE S_20_1_PRED_BOOL(V_20_1_DRAW_IF_VISIBLE_OR_NO_OVERFLOW) +#define PREDICATION_HINT_WAIT S_20_1_HINT(V_20_1_WAIT_UNTIL_FINAL_ZPASS_WRITTEN) +#define PREDICATION_HINT_NOWAIT_DRAW S_20_1_HINT(V_20_1_DRAW_IF_NOT_FINAL_ZPASS_WRITTEN) +#define PREDICATION_OP_CLEAR V_20_1_CLEAR_PREDICATE +#define PREDICATION_OP_ZPASS V_20_1_SET_ZPASS_PREDICATE +#define PREDICATION_OP_PRIMCOUNT V_20_1_SET_PRIMCOUNT_PREDICATE +#define PREDICATION_OP_BOOL64 V_20_1_DX12 +#define PREDICATION_OP_BOOL32 V_20_1_VULKAN +#define PREDICATION_CONTINUE S_20_1_CONTINUE_BIT(V_20_1_CONTINUE_SET_PREDICATION) #define PKT3_COND_EXEC 0x22 -#define COND_EXEC_USERQ_OVERRULE_CMD (1 << 31) #define PKT3_PRED_EXEC 0x23 #define PKT3_DRAW_INDIRECT 0x24 #define PKT3_DRAW_INDEX_INDIRECT 0x25 #define PKT3_INDEX_BASE 0x26 #define PKT3_DRAW_INDEX_2 0x27 #define PKT3_CONTEXT_CONTROL 0x28 -#define CC0_LOAD_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) -#define CC0_LOAD_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) -#define CC0_LOAD_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) -#define CC0_LOAD_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) -#define CC0_LOAD_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) -#define CC0_LOAD_CE_RAM(x) (((unsigned)(x)&0x1) << 28) -#define CC0_UPDATE_LOAD_ENABLES(x) (((unsigned)(x)&0x1) << 31) -#define CC1_SHADOW_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) -#define CC1_SHADOW_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) -#define CC1_SHADOW_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) -#define CC1_SHADOW_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) -#define CC1_SHADOW_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) -#define CC1_UPDATE_SHADOW_ENABLES(x) (((unsigned)(x)&0x1) << 31) #define PKT3_INDEX_TYPE 0x2A /* GFX6-8 */ #define PKT3_DRAW_INDIRECT_MULTI 0x2C -#define R_2C3_DRAW_INDEX_LOC 0x2C3 -#define S_2C3_THREAD_TRACE_MARKER_ENABLE(x) (((unsigned)(x)&0x1) << 29) -#define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x)&0x1) << 30) -#define S_2C3_DRAW_INDEX_ENABLE(x) (((unsigned)(x)&0x1) << 31) #define PKT3_DRAW_INDEX_AUTO 0x2D #define PKT3_DRAW_INDEX_IMMD 0x2E /* GFX6 only */ #define PKT3_NUM_INSTANCES 0x2F @@ -130,9 +95,6 @@ #define WAIT_REG_MEM_PFP (1 << 8) #define PKT3_MEM_WRITE 0x3D /* GFX6 only */ #define PKT3_INDIRECT_BUFFER 0x3F /* GFX6+ */ -#define S_3F3_INHERIT_VMID_MQD_GFX(x) (((unsigned)(x)&0x1) << 22) /* userqueue only */ -#define S_3F3_VALID_COMPUTE(x) (((unsigned)(x)&0x1) << 23) /* userqueue only */ -#define S_3F3_INHERIT_VMID_MQD_COMPUTE(x) (((unsigned)(x)&0x1) << 30) /* userqueue only */ #define PKT3_COPY_DATA 0x40 #define COPY_DATA_SRC_SEL(x) ((x)&0xf) #define COPY_DATA_REG 0 @@ -164,7 +126,7 @@ #define PKT3_ME_INITIALIZE 0x44 /* GFX6 only */ #define PKT3_COND_WRITE 0x45 #define PKT3_EVENT_WRITE 0x46 -#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_TYPE(x) S_46_1_EVENT_TYPE(x) /* 0 - any non-TS event * 1 - ZPASS_DONE * 2 - SAMPLE_PIPELINESTAT @@ -172,7 +134,7 @@ * 4 - *S_PARTIAL_FLUSH * 5 - TS events */ -#define EVENT_INDEX(x) ((x) << 8) +#define EVENT_INDEX(x) S_46_1_EVENT_INDEX(x) #define PIXEL_PIPE_STATE_CNTL_COUNTER_ID(x) ((x) << 3) #define PIXEL_PIPE_STATE_CNTL_STRIDE(x) ((x) << 9) /* 0 - 32 bits diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index c55244bb6e4..40c97feb890 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -10563,8 +10563,8 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer, bool index radeon_emit(0); radeon_emit(vertex_offset_reg); radeon_emit(start_instance_reg); - radeon_emit(draw_id_reg | S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) | S_2C3_COUNT_INDIRECT_ENABLE(!!count_va) | - S_2C3_THREAD_TRACE_MARKER_ENABLE(sqtt_en)); + radeon_emit(draw_id_reg | S_2C_4_DRAW_INDEX_ENABLE(draw_id_enable) | S_2C_4_COUNT_INDIRECT_ENABLE(!!count_va) | + S_2C_4_THREAD_TRACE_MARKER_ENABLE(sqtt_en)); radeon_emit(draw_count); /* count */ radeon_emit(count_va); /* count_addr */ radeon_emit(count_va >> 32); @@ -15008,7 +15008,7 @@ radv_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_vi if (va) { assert(pred_op == PREDICATION_OP_BOOL32 || pred_op == PREDICATION_OP_BOOL64); - op = PRED_OP(pred_op); + op = S_20_1_PRED_OP(pred_op); /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is zero, all * rendering commands are discarded. Otherwise, they are discarded if diff --git a/src/amd/vulkan/radv_dgc.c b/src/amd/vulkan/radv_dgc.c index eb22a5f870f..690f606c25b 100644 --- a/src/amd/vulkan/radv_dgc.c +++ b/src/amd/vulkan/radv_dgc.c @@ -1410,8 +1410,8 @@ dgc_emit_pkt3_draw_indirect(struct dgc_cmdbuf *cs, nir_def *has_drawid, bool ind dgc_cs_emit_imm(0); dgc_cs_emit(vertex_offset_reg); dgc_cs_emit(nir_bcsel(b, has_baseinstance, start_instance_reg, nir_imm_int(b, 0))); - dgc_cs_emit(nir_ior_imm(b, nir_ior(b, draw_id_reg, nir_imm_int(b, S_2C3_DRAW_INDEX_ENABLE(1))), - S_2C3_THREAD_TRACE_MARKER_ENABLE(sqtt_en))); + dgc_cs_emit(nir_ior_imm(b, nir_ior(b, draw_id_reg, nir_imm_int(b, S_2C_4_DRAW_INDEX_ENABLE(1))), + S_2C_4_THREAD_TRACE_MARKER_ENABLE(sqtt_en))); dgc_cs_emit_imm(1); /* draw count */ dgc_cs_emit_imm(0); /* count va low */ dgc_cs_emit_imm(0); /* count va high */ @@ -1542,7 +1542,7 @@ dgc_emit_draw_with_count(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *s nir_def *start_instance_reg = nir_bcsel(b, has_baseinstance, nir_iadd(b, vertex_offset_reg, start_instance_offset), nir_imm_int(b, 0)); nir_def *draw_id_reg = nir_bcsel( - b, has_drawid, nir_ior_imm(b, nir_iadd(b, vertex_offset_reg, nir_imm_int(b, 1)), S_2C3_DRAW_INDEX_ENABLE(1)), + b, has_drawid, nir_ior_imm(b, nir_iadd(b, vertex_offset_reg, nir_imm_int(b, 1)), S_2C_4_DRAW_INDEX_ENABLE(1)), nir_imm_int(b, 0)); nir_def *di_src_sel = nir_imm_int(b, indexed ? V_0287F0_DI_SRC_SEL_DMA : V_0287F0_DI_SRC_SEL_AUTO_INDEX); @@ -1555,7 +1555,7 @@ dgc_emit_draw_with_count(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *s dgc_cs_emit_imm(0); dgc_cs_emit(vertex_offset_reg); dgc_cs_emit(start_instance_reg); - dgc_cs_emit(nir_ior_imm(b, draw_id_reg, S_2C3_THREAD_TRACE_MARKER_ENABLE(sqtt_en))); + dgc_cs_emit(nir_ior_imm(b, draw_id_reg, S_2C_4_THREAD_TRACE_MARKER_ENABLE(sqtt_en))); dgc_cs_emit(draw_count); dgc_cs_emit_imm(0); dgc_cs_emit_imm(0); diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 01692c90f7a..0c08ae1e001 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -686,8 +686,8 @@ radv_emit_graphics(struct radv_device *device, struct radv_cmd_stream *cs) if (!device->uses_shadow_regs) { ac_pm4_cmd_add(pm4, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - ac_pm4_cmd_add(pm4, CC0_UPDATE_LOAD_ENABLES(1)); - ac_pm4_cmd_add(pm4, CC1_UPDATE_SHADOW_ENABLES(1)); + ac_pm4_cmd_add(pm4, S_28_1_UPDATE_LOAD_ENABLES(1)); + ac_pm4_cmd_add(pm4, S_28_2_UPDATE_SHADOW_ENABLES(1)); if (has_clear_state) { ac_pm4_cmd_add(pm4, PKT3(PKT3_CLEAR_STATE, 0, 0)); @@ -1545,7 +1545,7 @@ radv_create_perf_counter_lock_cs(struct radv_device *device, unsigned pass, bool if (!unlock) { uint64_t mutex_va = radv_buffer_get_va(device->perf_counter_bo) + PERF_CTR_BO_LOCK_OFFSET; - ac_emit_cp_atomic_mem(cs->b, TC_OP_ATOMIC_CMPSWAP_32, ATOMIC_COMMAND_LOOP, mutex_va, 1, 0); + ac_emit_cp_atomic_mem(cs->b, V_1E_1_GL2_OP_ATOMIC_CMPSWAP_32, V_1E_1_LOOP_UNTIL_COMPARE_SATISFIED, mutex_va, 1, 0); } uint64_t va = radv_buffer_get_va(device->perf_counter_bo) + PERF_CTR_BO_PASS_OFFSET; diff --git a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c index a20cedb1649..58d53eeb210 100644 --- a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c +++ b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c @@ -29,13 +29,13 @@ bool si_init_cp_reg_shadowing(struct si_context *sctx) } ac_pm4_cmd_add(shadowing_pm4, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - ac_pm4_cmd_add(shadowing_pm4, CC0_UPDATE_LOAD_ENABLES(1) | - CC0_LOAD_PER_CONTEXT_STATE(1) | CC0_LOAD_CS_SH_REGS(1) | - CC0_LOAD_GFX_SH_REGS(1) | CC0_LOAD_GLOBAL_UCONFIG(1)); - ac_pm4_cmd_add(shadowing_pm4, CC1_UPDATE_SHADOW_ENABLES(1) | - CC1_SHADOW_PER_CONTEXT_STATE(1) | CC1_SHADOW_CS_SH_REGS(1) | - CC1_SHADOW_GFX_SH_REGS(1) | CC1_SHADOW_GLOBAL_UCONFIG(1) | - CC1_SHADOW_GLOBAL_CONFIG(1)); + ac_pm4_cmd_add(shadowing_pm4, S_28_1_UPDATE_LOAD_ENABLES(1) | + S_28_1_LOAD_PER_CONTEXT_STATE(1) | S_28_1_LOAD_CS_SH_REGS(1) | + S_28_1_LOAD_GFX_SH_REGS(1) | S_28_1_LOAD_GLOBAL_UCONFIG(1)); + ac_pm4_cmd_add(shadowing_pm4, S_28_2_UPDATE_SHADOW_ENABLES(1) | + S_28_2_SHADOW_PER_CONTEXT_STATE(1) | S_28_2_SHADOW_CS_SH_REGS(1) | + S_28_2_SHADOW_GFX_SH_REGS(1) | S_28_2_SHADOW_GLOBAL_UCONFIG(1) | + S_28_2_SHADOW_GLOBAL_CONFIG(1)); for (unsigned i = 0; i < SI_NUM_REG_RANGES; i++) ac_build_load_reg(&sctx->screen->info, shadowing_pm4, i, diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c index 444e0141677..112684b90c0 100644 --- a/src/gallium/drivers/radeonsi/si_query.c +++ b/src/gallium/drivers/radeonsi/si_query.c @@ -1083,7 +1083,7 @@ static void si_emit_query_predication(struct si_context *ctx, unsigned index) struct gfx11_sh_query *gfx10_query = (struct gfx11_sh_query *)query; struct gfx11_sh_query_buffer *qbuf, *first, *last; - op = PRED_OP(PREDICATION_OP_PRIMCOUNT); + op = S_20_1_PRED_OP(PREDICATION_OP_PRIMCOUNT); /* if true then invert, see GL_ARB_conditional_render_inverted */ if (!invert) @@ -1131,17 +1131,17 @@ static void si_emit_query_predication(struct si_context *ctx, unsigned index) struct si_query_buffer *qbuf; if (query->workaround_buf) { - op = PRED_OP(PREDICATION_OP_BOOL64); + op = S_20_1_PRED_OP(PREDICATION_OP_BOOL64); } else { switch (query->b.type) { case PIPE_QUERY_OCCLUSION_COUNTER: case PIPE_QUERY_OCCLUSION_PREDICATE: case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: - op = PRED_OP(PREDICATION_OP_ZPASS); + op = S_20_1_PRED_OP(PREDICATION_OP_ZPASS); break; case PIPE_QUERY_SO_OVERFLOW_PREDICATE: case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE: - op = PRED_OP(PREDICATION_OP_PRIMCOUNT); + op = S_20_1_PRED_OP(PREDICATION_OP_PRIMCOUNT); invert = !invert; break; default: diff --git a/src/gallium/drivers/radeonsi/si_sqtt.c b/src/gallium/drivers/radeonsi/si_sqtt.c index a1b892776c6..30ca743d831 100644 --- a/src/gallium/drivers/radeonsi/si_sqtt.c +++ b/src/gallium/drivers/radeonsi/si_sqtt.c @@ -107,8 +107,8 @@ static void si_sqtt_start(struct si_context *sctx, struct radeon_cmdbuf *cs) switch (ip_type) { case AMD_IP_GFX: radeon_emit(PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - radeon_emit(CC0_UPDATE_LOAD_ENABLES(1)); - radeon_emit(CC1_UPDATE_SHADOW_ENABLES(1)); + radeon_emit(S_28_1_UPDATE_LOAD_ENABLES(1)); + radeon_emit(S_28_2_UPDATE_SHADOW_ENABLES(1)); break; case AMD_IP_COMPUTE: radeon_emit(PKT3(PKT3_NOP, 0, 0)); @@ -160,8 +160,8 @@ static void si_sqtt_stop(struct si_context *sctx, struct radeon_cmdbuf *cs) switch (ip_type) { case AMD_IP_GFX: radeon_emit(PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - radeon_emit(CC0_UPDATE_LOAD_ENABLES(1)); - radeon_emit(CC1_UPDATE_SHADOW_ENABLES(1)); + radeon_emit(S_28_1_UPDATE_LOAD_ENABLES(1)); + radeon_emit(S_28_2_UPDATE_SHADOW_ENABLES(1)); break; case AMD_IP_COMPUTE: radeon_emit(PKT3(PKT3_NOP, 0, 0)); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index bb4c93c4b17..54f7c63bacc 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4866,8 +4866,8 @@ static bool gfx6_init_gfx_preamble_state(struct si_context *sctx) if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) { ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1)); - ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1)); + ac_pm4_cmd_add(&pm4->base, S_28_1_UPDATE_LOAD_ENABLES(1)); + ac_pm4_cmd_add(&pm4->base, S_28_2_UPDATE_SHADOW_ENABLES(1)); if (sscreen->dpbb_allowed) { ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0)); @@ -4956,17 +4956,17 @@ static bool gfx10_init_gfx_preamble_state(struct si_context *sctx) */ if (sctx->gfx_level != GFX11_5) { ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1) | CC0_LOAD_PER_CONTEXT_STATE(1) | - CC0_LOAD_CS_SH_REGS(1) | CC0_LOAD_GFX_SH_REGS(1) | - CC0_LOAD_GLOBAL_UCONFIG(1)); - ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1) | CC1_SHADOW_PER_CONTEXT_STATE(1) | - CC1_SHADOW_CS_SH_REGS(1) | CC1_SHADOW_GFX_SH_REGS(1) | - CC1_SHADOW_GLOBAL_UCONFIG(1) | CC1_SHADOW_GLOBAL_CONFIG(1)); + ac_pm4_cmd_add(&pm4->base, S_28_1_UPDATE_LOAD_ENABLES(1) | S_28_1_LOAD_PER_CONTEXT_STATE(1) | + S_28_1_LOAD_CS_SH_REGS(1) | S_28_1_LOAD_GFX_SH_REGS(1) | + S_28_1_LOAD_GLOBAL_UCONFIG(1)); + ac_pm4_cmd_add(&pm4->base, S_28_2_UPDATE_SHADOW_ENABLES(1) | S_28_2_SHADOW_PER_CONTEXT_STATE(1) | + S_28_2_SHADOW_CS_SH_REGS(1) | S_28_2_SHADOW_GFX_SH_REGS(1) | + S_28_2_SHADOW_GLOBAL_UCONFIG(1) | S_28_2_SHADOW_GLOBAL_CONFIG(1)); } } else if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) { ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1)); - ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1)); + ac_pm4_cmd_add(&pm4->base, S_28_1_UPDATE_LOAD_ENABLES(1)); + ac_pm4_cmd_add(&pm4->base, S_28_2_UPDATE_SHADOW_ENABLES(1)); if (sscreen->dpbb_allowed) { ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0)); @@ -5037,16 +5037,16 @@ static bool gfx12_init_gfx_preamble_state(struct si_context *sctx) if (sctx->uses_userq_reg_shadowing) { ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1) | CC0_LOAD_PER_CONTEXT_STATE(1) | - CC0_LOAD_CS_SH_REGS(1) | CC0_LOAD_GFX_SH_REGS(1) | - CC0_LOAD_GLOBAL_UCONFIG(1)); - ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1) | CC1_SHADOW_PER_CONTEXT_STATE(1) | - CC1_SHADOW_CS_SH_REGS(1) | CC1_SHADOW_GFX_SH_REGS(1) | - CC1_SHADOW_GLOBAL_UCONFIG(1) | CC1_SHADOW_GLOBAL_CONFIG(1)); + ac_pm4_cmd_add(&pm4->base, S_28_1_UPDATE_LOAD_ENABLES(1) | S_28_1_LOAD_PER_CONTEXT_STATE(1) | + S_28_1_LOAD_CS_SH_REGS(1) | S_28_1_LOAD_GFX_SH_REGS(1) | + S_28_1_LOAD_GLOBAL_UCONFIG(1)); + ac_pm4_cmd_add(&pm4->base, S_28_2_UPDATE_SHADOW_ENABLES(1) | S_28_2_SHADOW_PER_CONTEXT_STATE(1) | + S_28_2_SHADOW_CS_SH_REGS(1) | S_28_2_SHADOW_GFX_SH_REGS(1) | + S_28_2_SHADOW_GLOBAL_UCONFIG(1) | S_28_2_SHADOW_GLOBAL_CONFIG(1)); } else if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) { ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); - ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1)); - ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1)); + ac_pm4_cmd_add(&pm4->base, S_28_1_UPDATE_LOAD_ENABLES(1)); + ac_pm4_cmd_add(&pm4->base, S_28_2_UPDATE_SHADOW_ENABLES(1)); } if (sctx->is_gfx_queue && sscreen->dpbb_allowed && !sctx->uses_userq_reg_shadowing) { diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 25c5d444692..9410e84b56e 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -1610,8 +1610,8 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw radeon_emit((sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); radeon_emit((sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); radeon_emit(((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) | - S_2C3_DRAW_INDEX_ENABLE(sctx->vs_uses_draw_id) | - S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count)); + S_2C_4_DRAW_INDEX_ENABLE(sctx->vs_uses_draw_id) | + S_2C_4_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count)); radeon_emit(indirect->draw_count); radeon_emit(count_va); radeon_emit(count_va >> 32); diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp index 678f15bc2b0..7e5ee667c88 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp @@ -1495,17 +1495,17 @@ static void amdgpu_cs_add_userq_packets(struct amdgpu_winsys *aws, amdgpu_pkt_add_dw(PKT3(PKT3_INDIRECT_BUFFER, 2, 0)); amdgpu_pkt_add_dw(amdgpu_bo_get_va(userq->f32_shadowing_ib_bo)); amdgpu_pkt_add_dw(amdgpu_bo_get_va(userq->f32_shadowing_ib_bo) >> 32); - amdgpu_pkt_add_dw(userq->f32_shadowing_ib_pm4_dw | S_3F3_INHERIT_VMID_MQD_GFX(1)); + amdgpu_pkt_add_dw(userq->f32_shadowing_ib_pm4_dw | S_3F_3_INHERIT_VMID_PFP(1)); } amdgpu_pkt_add_dw(PKT3(PKT3_INDIRECT_BUFFER, 2, 0)); amdgpu_pkt_add_dw(csc->chunk_ib[IB_MAIN].va_start); amdgpu_pkt_add_dw(csc->chunk_ib[IB_MAIN].va_start >> 32); if (userq->ip_type == AMD_IP_GFX) - amdgpu_pkt_add_dw((csc->chunk_ib[IB_MAIN].ib_bytes / 4) | S_3F3_INHERIT_VMID_MQD_GFX(1)); + amdgpu_pkt_add_dw((csc->chunk_ib[IB_MAIN].ib_bytes / 4) | S_3F_3_INHERIT_VMID_PFP(1)); else - amdgpu_pkt_add_dw((csc->chunk_ib[IB_MAIN].ib_bytes / 4) | S_3F3_VALID_COMPUTE(1) | - S_3F3_INHERIT_VMID_MQD_COMPUTE(1)); + amdgpu_pkt_add_dw((csc->chunk_ib[IB_MAIN].ib_bytes / 4) | S_3F_3_VALID(1) | + S_3F_3_INHERIT_VMID_MEC(1)); /* Add 8 for release mem packet and 2 for protected fence signal packet. * Calculcating userq_fence_seq_num this way to match with kernel fence that is @@ -1549,7 +1549,7 @@ static void amdgpu_cs_add_userq_packets(struct amdgpu_winsys *aws, for (unsigned i = 0; i < 1 + DIV_ROUND_UP(num_fences, 4); i++) *cond_exec_skip_counts[i].count_dw_ptr = (amdgpu_pkt_get_next_wptr() - cond_exec_skip_counts[i].start_wptr) | - COND_EXEC_USERQ_OVERRULE_CMD; + S_22_4_EXEC_USERQ_OVERRULE_CMD(1); } } else { mesa_loge("amdgpu: unsupported userq ip submission = %d\n", userq->ip_type); diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_userq.c b/src/gallium/winsys/amdgpu/drm/amdgpu_userq.c index e92ad158cec..49c20ea0131 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_userq.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_userq.c @@ -320,7 +320,7 @@ amdgpu_userq_submit_cs_preamble_ib_once(struct radeon_cmdbuf *rcs, struct ac_pm4 amdgpu_pkt_add_dw(PKT3(PKT3_INDIRECT_BUFFER, 2, 0)); amdgpu_pkt_add_dw(amdgpu_bo_get_va(userq->cs_preamble_ib_bo)); amdgpu_pkt_add_dw(amdgpu_bo_get_va(userq->cs_preamble_ib_bo) >> 32); - amdgpu_pkt_add_dw(pm4->ndw | S_3F3_INHERIT_VMID_MQD_GFX(1)); + amdgpu_pkt_add_dw(pm4->ndw | S_3F_3_INHERIT_VMID_PFP(1)); amdgpu_pkt_end(); simple_mtx_unlock(&userq->lock); @@ -367,7 +367,7 @@ amdgpu_userq_f32_init_reg_shadowing(struct radeon_cmdbuf *rcs, struct ac_pm4_sta amdgpu_pkt_add_dw(PKT3(PKT3_INDIRECT_BUFFER, 2, 0)); amdgpu_pkt_add_dw(amdgpu_bo_get_va(userq->f32_shadowing_ib_bo)); amdgpu_pkt_add_dw(amdgpu_bo_get_va(userq->f32_shadowing_ib_bo) >> 32); - amdgpu_pkt_add_dw(pm4->ndw | S_3F3_INHERIT_VMID_MQD_GFX(1)); + amdgpu_pkt_add_dw(pm4->ndw | S_3F_3_INHERIT_VMID_PFP(1)); amdgpu_pkt_end(); simple_mtx_unlock(&userq->lock);