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This commit is contained in:
Dave Airlie 2009-01-29 20:46:31 +10:00
parent c9bb5cd20e
commit 70661f678e
7 changed files with 195 additions and 7 deletions
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2
src/mesa/drivers/dri/r300/r300_swtcl.c
View file

@ -303,7 +303,7 @@ r300AllocDmaLowVerts( r300ContextPtr rmesa, int nverts, int vsize )
ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim );
ASSERT( rmesa->radeon.dma.current_used +
rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
rmesa->dma.current_vertexptr );
rmesa->radeon.dma.current_vertexptr );
// fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr,
// rmesa->radeon.dma.current_vertexptr);

22
src/mesa/drivers/dri/radeon/common_cmdbuf.h
View file

@ -14,6 +14,28 @@ void rcommonBeginBatch(radeonContextPtr rmesa,
const char *function,
int line);
#define RADEON_CP_PACKET3_NOP 0xC0001000
#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
#define CP_PACKET2 (2 << 30)
#define CP_PACKET0(reg, n) (RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
#define CP_PACKET0_ONE(reg, n) (RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))

14
src/mesa/drivers/dri/radeon/common_context.h
View file

@ -247,6 +247,19 @@ struct radeon_dma {
GLuint nr_released_bufs;
};
/* radeon_swtcl.c
*/
struct radeon_swtcl_info {
struct radeon_bo *bo;
/* Fallback rasterization functions
*/
GLuint hw_primitive;
GLenum render_primitive;
GLuint numverts;
};
struct radeon_ioctl {
GLuint vertex_offset;
GLuint vertex_size;
@ -403,6 +416,7 @@ struct radeon_context {
/* Derived state - for r300 only */
struct radeon_state state;
struct radeon_swtcl swtcl;
/* Configuration cache
*/
driOptionCache optionCache;

62
src/mesa/drivers/dri/radeon/common_misc.c
View file

@ -2389,4 +2389,66 @@ void radeonReleaseDmaRegion(radeonContextPtr rmesa)
radeon_bo_unref(rmesa->dma.current);
rmesa->dma.current = NULL;
}
void rcommonEmitVertexAOS(radeonContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset)
{
BATCH_LOCALS(rmesa);
if (RADEON_DEBUG & DEBUG_VERTS)
fprintf(stderr, "%s: vertex_size %d, offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
BEGIN_BATCH(5);
OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2);
OUT_BATCH(1);
OUT_BATCH(vertex_size | (vertex_size << 8));
OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
}
void rcommonEmitVbufPrim(radeonContextPtr rmesa, GLuint primitive, GLuint vertex_nr)
{
BATCH_LOCALS(rmesa);
int type, num_verts;
type = r300PrimitiveType(rmesa, primitive);
num_verts = r300NumVerts(rmesa, vertex_nr, primitive);
BEGIN_BATCH(3);
OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
END_BATCH();
}
/* Alloc space in the current dma region.
*/
static void *
rcommonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize )
{
GLuint bytes = vsize * nverts;
void *head;
if (!rmesa->dma.current || rmesa->dma.current_vertexptr + bytes > rmesa->dma.current->size) {
radeonRefillCurrentDmaRegion( rmesa, bytes);
}
if (!rmesa->dma.flush) {
rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
rmesa->dma.flush = flush_last_swtcl_prim;
}
ASSERT( vsize == rmesa->swtcl.vertex_size * 4 );
ASSERT( rmesa->radeon.dma.flush == flush_last_swtcl_prim );
ASSERT( rmesa->radeon.dma.current_used +
rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
rmesa->radeon.dma.current_vertexptr );
// fprintf(stderr,"current %p %x\n", rmesa->radeon.dma.current->ptr,
// rmesa->radeon.dma.current_vertexptr);
head = (rmesa->radeon.dma.current->ptr + rmesa->radeon.dma.current_vertexptr);
rmesa->radeon.dma.current_vertexptr += bytes;
rmesa->swtcl.numverts += nverts;
return head;
}

7
src/mesa/drivers/dri/radeon/radeon_tcl.c
View file

@ -177,18 +177,17 @@ static void radeonEmitPrim( GLcontext *ctx,
r100ContextPtr rmesa = R100_CONTEXT( ctx );
radeonTclPrimitive( ctx, prim, hwprim );
radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
rmesa->hw.max_state_size + VBUF_BUFSZ );
rcommonEnsureCmdBufSpace( &rmesa->radeon,
AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
rmesa->hw.max_state_size + VBUF_BUFSZ );
radeonEmitAOS( rmesa,
rmesa->tcl.aos_components,
rmesa->tcl.nr_aos_components,
start );
/* Why couldn't this packet have taken an offset param?
*/
radeonEmitVbufPrim( rmesa,
rmesa->tcl.vertex_format,
rmesa->tcl.hw_primitive,
count - start );
}

92
src/mesa/drivers/dri/radeon/radeon_texstate.c
View file

@ -122,6 +122,7 @@ tx_table[] =
* \param tObj GL texture object whose images are to be posted to
* hardware state.
*/
#if 0
static void radeonSetTexImages( r100ContextPtr rmesa,
struct gl_texture_object *tObj )
{
@ -354,7 +355,7 @@ static void radeonSetTexImages( r100ContextPtr rmesa,
/* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */
}
#endif
/* ================================================================
@ -1100,7 +1101,7 @@ static GLboolean radeon_validate_texgen( GLcontext *ctx, GLuint unit )
return GL_TRUE;
}
#if 0
static void disable_tex( GLcontext *ctx, int unit )
{
r100ContextPtr rmesa = R100_CONTEXT(ctx);
@ -1332,9 +1333,89 @@ static GLboolean update_tex_common( GLcontext *ctx, int unit )
FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback );
return !t->border_fallback;
}
#endif
/**
* Compute the cached hardware register values for the given texture object.
*
* \param rmesa Context pointer
* \param t the r300 texture object
*/
static void setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t)
{
const struct gl_texture_image *firstImage =
t->base.Image[0][t->mt->firstLevel];
GLint log2Width, log2Height, log2Depth, texelBytes;
log2Width = firstImage->WidthLog2;
log2Height = firstImage->HeightLog2;
log2Depth = firstImage->DepthLog2;
texelBytes = firstImage->TexFormat->TexelBytes;
if (!t->image_override) {
if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) {
const struct tx_table *table = _mesa_little_endian() ? tx_table_le :
tx_table_be;
t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
RADEON_TXFORMAT_ALPHA_IN_MAP);
t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
// t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format;
// t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter;
} else {
_mesa_problem(NULL, "unexpected texture format in %s",
__FUNCTION__);
return;
}
}
t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK;
t->pp_txfilter |= (t->mt->lastLevel - t->mt->firstLevel) << RADEON_MAX_MIP_LEVEL_SHIFT;
t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK |
RADEON_TXFORMAT_HEIGHT_MASK |
RADEON_TXFORMAT_CUBIC_MAP_ENABLE |
RADEON_TXFORMAT_F5_WIDTH_MASK |
RADEON_TXFORMAT_F5_HEIGHT_MASK);
t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) |
(log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT));
t->tile_bits = 0;
if (t->base.Target == GL_TEXTURE_CUBE_MAP) {
ASSERT(log2Width == log2Height);
t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) |
(log2Height << RADEON_TXFORMAT_F5_HEIGHT_SHIFT) |
/* don't think we need this bit, if it exists at all - fglrx does not set it */
(RADEON_TXFORMAT_CUBIC_MAP_ENABLE));
t->pp_cubic_faces = ((log2Width << RADEON_FACE_WIDTH_1_SHIFT) |
(log2Height << RADEON_FACE_HEIGHT_1_SHIFT) |
(log2Width << RADEON_FACE_WIDTH_2_SHIFT) |
(log2Height << RADEON_FACE_HEIGHT_2_SHIFT) |
(log2Width << RADEON_FACE_WIDTH_3_SHIFT) |
(log2Height << RADEON_FACE_HEIGHT_3_SHIFT) |
(log2Width << RADEON_FACE_WIDTH_4_SHIFT) |
(log2Height << RADEON_FACE_HEIGHT_4_SHIFT));
}
t->pp_txsize = (((firstImage->Width - 1) << RADEON_PP_TX_WIDTHMASK_SHIFT)
| ((firstImage->Height - 1) << RADEON_PP_TX_HEIGHTMASK_SHIFT));
if ( !t->image_override ) {
if (firstImage->IsCompressed)
t->pp_txpitch = (firstImage->Width + 63) & ~(63);
else
t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63);
t->pp_txpitch -= 32;
}
if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
}
}
#if 0
static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
{
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
@ -1359,6 +1440,13 @@ static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
return GL_TRUE;
}
}
#endif
static GLboolean radeonUpdateTextureUnit( GLcontext *ctx, int unit )
{
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
}
void radeonUpdateTextureState( GLcontext *ctx )
{

3
src/mesa/drivers/dri/radeon/server/radeon_reg.h
View file

@ -2031,6 +2031,9 @@
#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
#define R200_CP_CMD_3D_DRAW_VBUF_2 0xC0003400
#define R200_CP_CMD_3D_DRAW_IMMD_2 0xC0003500
#define R200_CP_CMD_3D_DRAW_INDX_2 0xC0003600
#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300