fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-02-23 16:10:33 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

radeonsi: handle VGT_GS_OUT_PRIM_TYPE like a tracked register

Browse source 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23687>
This commit is contained in:
Marek Olšák 2023-06-06 12:40:20 -04:00 • committed by Marge Bot
parent 315231b5a5
commit 7065bbdc23
5 changed files with 11 additions and 17 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -289,6 +289,7 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_ITEMSIZE] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_MODE] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL] = 0x1e;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GS_OUT_PRIM_TYPE] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_1] = 0;
ctx->tracked_regs.context_reg_value[SI_TRACKED_VGT_GSVS_RING_OFFSET_2] = 0;
@ -306,11 +307,6 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
/* Set all cleared context registers to saved. */
ctx->tracked_regs.context_reg_saved_mask = BITFIELD64_MASK(SI_NUM_TRACKED_CONTEXT_REGS);
if (ctx->gfx_level >= GFX11)
ctx->last_gs_out_prim = -1; /* uconfig register, unknown value */
else
ctx->last_gs_out_prim = 0; /* context register cleared by CLEAR_STATE */
}
void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_vbo_func wrapper,
@ -532,7 +528,6 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
} else {
/* Set all register values to unknown. */
ctx->tracked_regs.context_reg_saved_mask = 0;
ctx->last_gs_out_prim = -1; /* unknown */
}
/* 0xffffffff is an impossible value to register SPI_PS_INPUT_CNTL_n */

1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1159,7 +1159,6 @@ struct si_context {
unsigned last_restart_index;
unsigned last_prim;
unsigned last_multi_vgt_param;
unsigned last_gs_out_prim;
unsigned current_vs_state; /* all VS bits including LS bits */
unsigned current_gs_state; /* only GS and NGG bits */
unsigned last_vs_state;

2
src/gallium/drivers/radeonsi/si_state.h
View file

@ -299,6 +299,7 @@ enum si_tracked_context_reg
SI_TRACKED_VGT_GSVS_RING_ITEMSIZE, /* GFX6-10 (GFX11+ can reuse this slot) */
SI_TRACKED_VGT_GS_MODE, /* GFX6-10 (GFX11+ can reuse this slot) */
SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, /* GFX6-10 (GFX11+ can reuse this slot) */
SI_TRACKED_VGT_GS_OUT_PRIM_TYPE, /* GFX6-10 (GFX11+ can reuse this slot) */
/* 3 consecutive registers */
SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* GFX6-10 (GFX11+ can reuse this slot) */
@ -324,6 +325,7 @@ enum si_tracked_other_reg {
SI_TRACKED_GE_PC_ALLOC, /* GFX10+ */
SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, /* GFX7+ */
SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS, /* GFX10+ */
SI_TRACKED_VGT_GS_OUT_PRIM_TYPE_UCONFIG, /* GFX11+ */
SI_TRACKED_COMPUTE_RESOURCE_LIMITS,
SI_TRACKED_COMPUTE_NUM_THREAD_X,

15
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -1182,13 +1182,14 @@ static void si_emit_rasterizer_prim_state(struct si_context *sctx)
value);
}
unsigned gs_out_prim = sctx->gs_out_prim;
if (unlikely(gs_out_prim != sctx->last_gs_out_prim && (NGG || HAS_GS))) {
if (GFX_VERSION >= GFX11)
radeon_set_uconfig_reg(R_030998_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
else
radeon_set_context_reg(R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
sctx->last_gs_out_prim = gs_out_prim;
if (NGG || HAS_GS) {
if (GFX_VERSION >= GFX11) {
radeon_opt_set_uconfig_reg(sctx, R_030998_VGT_GS_OUT_PRIM_TYPE,
SI_TRACKED_VGT_GS_OUT_PRIM_TYPE_UCONFIG, sctx->gs_out_prim);
} else {
radeon_opt_set_context_reg(sctx, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
SI_TRACKED_VGT_GS_OUT_PRIM_TYPE, sctx->gs_out_prim);
}
}
if (GFX_VERSION == GFX9)

3
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -3406,7 +3406,6 @@ bool si_update_ngg(struct si_context *sctx)
}
sctx->ngg = new_ngg;
sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
si_select_draw_vbo(sctx);
return true;
}
@ -3431,7 +3430,6 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
si_update_common_shader_state(sctx, sel, PIPE_SHADER_GEOMETRY);
si_select_draw_vbo(sctx);
sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
ngg_changed = si_update_ngg(sctx);
if (ngg_changed || enable_changed)
@ -3494,7 +3492,6 @@ static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
si_update_common_shader_state(sctx, sel, PIPE_SHADER_TESS_EVAL);
si_select_draw_vbo(sctx);
sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
bool ngg_changed = si_update_ngg(sctx);
if (ngg_changed || enable_changed)