From 701eb1ce8daf4ed452da7cb5314a830dca669bfb Mon Sep 17 00:00:00 2001
From: Rob Clark <rob.clark@oss.qualcomm.com>
Date: Sun, 2 Nov 2025 09:28:42 -0800
Subject: [PATCH] freedreno/a6xx: Emit RB buffer setup for sysmem too

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
---
 .../drivers/freedreno/a6xx/fd6_gmem.cc        | 33 +++++++++++++++----
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
index 01da7389cad..d6afd800cb0 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
@@ -1022,15 +1022,30 @@ static void prepare_tile_fini(struct fd_batch *batch);
 
 template <chip CHIP>
 static void
-fd7_emit_static_binning_regs(fd_cs &cs)
+fd7_emit_static_binning_regs(fd_cs &cs, bool gmem)
 {
-   fd_ncrb<CHIP> ncrb(cs, 5);
+   bool sysmem = !gmem;
+   fd_ncrb<CHIP> ncrb(cs, 4);
 
-   ncrb.add(RB_BUFFER_CNTL(CHIP));
-   ncrb.add(RB_CCU_DBG_ECO_CNTL(CHIP, 0x0));
+   assert(CHIP >= A7XX);
+
+   ncrb.add(RB_BUFFER_CNTL(CHIP,
+      .z_sysmem = sysmem,
+      .s_sysmem = sysmem,
+      .rt0_sysmem = sysmem,
+      .rt1_sysmem = sysmem,
+      .rt2_sysmem = sysmem,
+      .rt3_sysmem = sysmem,
+      .rt4_sysmem = sysmem,
+      .rt5_sysmem = sysmem,
+      .rt6_sysmem = sysmem,
+      .rt7_sysmem = sysmem,
+   ));
    ncrb.add(GRAS_LRZ_CB_CNTL(CHIP, 0x0));
    ncrb.add(GRAS_MODE_CNTL(CHIP, 0x2));
-   ncrb.add(RB_CLEAR_TARGET(CHIP, .clear_mode = CLEAR_MODE_GMEM));
+   ncrb.add(RB_CLEAR_TARGET(CHIP,
+      .clear_mode = gmem ? CLEAR_MODE_GMEM : CLEAR_MODE_SYSMEM,
+   ));
 }
 
 template <chip CHIP>
@@ -1045,7 +1060,7 @@ fd6_build_preemption_preamble(struct fd_context *ctx)
    fd6_emit_gmem_cache_cntl<CHIP>(cs, screen, true);
 
    if (CHIP >= A7XX) {
-      fd7_emit_static_binning_regs<CHIP>(cs);
+      fd7_emit_static_binning_regs<CHIP>(cs, true);
    }
 
    /* TODO use CP_MEM_TO_SCRATCH_MEM on a7xx. The VSC scratch mem should be
@@ -1110,7 +1125,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
    patch_fb_read_gmem(batch);
 
    if (CHIP >= A7XX) {
-      fd7_emit_static_binning_regs<CHIP>(cs);
+      fd7_emit_static_binning_regs<CHIP>(cs, true);
    }
 
    if (use_hw_binning(batch)) {
@@ -2051,6 +2066,10 @@ fd6_emit_sysmem(struct fd_batch *batch)
 
    fd6_emit_gmem_cache_cntl<CHIP>(cs, screen, false);
 
+   if (CHIP >= A7XX) {
+      fd7_emit_static_binning_regs<CHIP>(cs, false);
+   }
+
    foreach_subpass (subpass, batch) {
       if (subpass->fast_cleared) {
          unsigned flushes = 0;