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i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.

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This was probably disabled due to a combination of several bugs in the
generator code (fixed earlier in this series) and a misunderstanding
of the hardware spec.  The documentation for most control flow
instructions mentions among other restrictions:

 "Instruction compression is not allowed."

This however doesn't have any implications on 16 wide not being
supported, because none of the control flow instructions have
multi-register operands (control flow instructions are not compressed
on more recent hardware either, except maybe SNB's IF with inline
compare).  In fact Gen4-5 had 16-wide control flow masks and stacks,
and the spec mentions in several places that control flow instructions
push and pop 16 channels worth of data -- Otherwise there doesn't seem
to be any indication that it shouldn't work.

Causes no piglit regressions, and gives the following shader-db
results on ILK:

 total instructions in shared programs: 4711384 -> 4711384 (0.00%)
 instructions in affected programs:     0 -> 0
 helped:                                0
 HURT:                                  0
 GAINED:                                1215
 LOST:                                  0

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2015-07-06 18:55:26 +03:00
parent 24842e18aa
commit 7009e2683e
1 changed files with 1 additions and 7 deletions
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8
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
View file

@ -417,18 +417,12 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
bld.emit(BRW_OPCODE_ENDIF);
if (!try_replace_with_sel() && devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
try_replace_with_sel();
}
void
fs_visitor::nir_emit_loop(nir_loop *loop)
{
if (devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
bld.emit(BRW_OPCODE_DO);
nir_emit_cf_list(&loop->body);