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winsys/amdgpu: Use amdgpu_winsys helper instead of open-coded casts

Browse source 
Cleanup to prevent breakage with the next change, no functional change
intended in this one.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
Michel Dänzer 2019-07-01 09:20:11 +02:00 • committed by Michel Dänzer
parent e06bc0b166
commit 6fce296400
3 changed files with 8 additions and 8 deletions
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2
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
View file

@ -743,7 +743,7 @@ static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type)
static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs,
enum ib_type ib_type)
{
struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
struct amdgpu_winsys *aws = amdgpu_winsys(ws);
/* Small IBs are better than big IBs, because the GPU goes idle quicker
* and there is less waiting for buffers and fences. Proof:
* http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1

2
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -66,7 +66,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
enum radeon_surf_mode mode,
struct radeon_surf *surf)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
int r;
r = amdgpu_surface_sanity(tex);

12
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -125,7 +125,7 @@ static void do_winsys_deinit(struct amdgpu_winsys *ws)
static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
if (ws->reserve_vmid)
amdgpu_vm_unreserve_vmid(ws->dev, 0);
@ -149,7 +149,7 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
struct radeon_info *info)
{
*info = ((struct amdgpu_winsys *)rws)->info;
*info = amdgpu_winsys(rws)->info;
}
static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
@ -162,7 +162,7 @@ static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
enum radeon_value_id value)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_heap_info heap;
uint64_t retval = 0;
@ -228,7 +228,7 @@ static bool amdgpu_read_registers(struct radeon_winsys *rws,
unsigned reg_offset,
unsigned num_registers, uint32_t *out)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
0xffffffff, 0, out) == 0;
@ -246,7 +246,7 @@ static int compare_pointers(void *key1, void *key2)
static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
bool destroy;
/* When the reference counter drops to zero, remove the device pointer
@ -272,7 +272,7 @@ static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
static void amdgpu_pin_threads_to_L3_cache(struct radeon_winsys *rws,
unsigned cache)
{
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
util_pin_thread_to_L3(ws->cs_queue.threads[0], cache,
util_cpu_caps.cores_per_L3);