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r600: Fix typos.

Browse source 
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8293>
This commit is contained in:
Vinson Lee 2021-01-01 17:31:15 -08:00 • committed by Marge Bot
parent 2944b4b6b4
commit 6fc3363368
35 changed files with 79 additions and 79 deletions
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2
src/gallium/drivers/r600/compute_memory_pool.c
View file

@ -495,7 +495,7 @@ static void compute_memory_move_item(struct compute_memory_pool *pool,
}
/**
* Frees the memory asociated to the item with id \a id from the pool.
* Frees the memory associated to the item with id \a id from the pool.
* \param id The id of the item to be freed.
*/
void compute_memory_free(struct compute_memory_pool* pool, int64_t id)

2
src/gallium/drivers/r600/compute_memory_pool.h
View file

@ -47,7 +47,7 @@ struct compute_memory_item
int64_t start_in_dw;
int64_t size_in_dw; /**< Size of the chunk in dwords */
/** Intermediate buffer asociated with an item. It is used mainly for mapping
/** Intermediate buffer associated with an item. It is used mainly for mapping
* items against it. They are listed in the pool's unallocated list */
struct r600_resource *real_buffer;

2
src/gallium/drivers/r600/evergreen_compute.c
View file

@ -1288,7 +1288,7 @@ static void r600_compute_global_transfer_unmap(struct pipe_context *ctx,
* to an offset within the compute memory pool. The function
* r600_compute_global_transfer_map() maps the memory pool
* resource rather than the struct r600_resource_global passed to
* it as an argument and then initalizes ptransfer->resource with
* it as an argument and then initializes ptransfer->resource with
* the memory pool resource (via pipe_buffer_map_range).
* When transfer_unmap is called it uses the memory pool's
* vtable which calls r600_buffer_transfer_map() rather than

4
src/gallium/drivers/r600/evergreen_state.c
View file

@ -1252,7 +1252,7 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx,
color->info |= S_028C70_COMPRESSION(1);
}
/* EXPORT_NORM is an optimzation that can be enabled for better
/* EXPORT_NORM is an optimization that can be enabled for better
* performance in certain cases.
* EXPORT_NORM can be enabled if:
* - 11-bit or smaller UNORM/SNORM/SRGB
@ -1282,7 +1282,7 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx,
}
/**
* This function intializes the CB* register values for RATs. It is meant
* This function initializes the CB* register values for RATs. It is meant
* to be used for 1D aligned buffers that do not have an associated
* radeon_surf.
*/

2
src/gallium/drivers/r600/r600_hw_context.c
View file

@ -44,7 +44,7 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
ctx->b.gfx.flush(ctx, PIPE_FLUSH_ASYNC, NULL);
return;
}
/* all will be accounted once relocation are emited */
/* all will be accounted once relocation are emitted */
ctx->b.gtt = 0;
ctx->b.vram = 0;

2
src/gallium/drivers/r600/r600_state.c
View file

@ -908,7 +908,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
S_0280A0_NUMBER_TYPE(ntype) |
S_0280A0_ENDIAN(endian);
/* EXPORT_NORM is an optimzation that can be enabled for better
/* EXPORT_NORM is an optimization that can be enabled for better
* performance in certain cases
*/
if (rctx->b.chip_class == R600) {

2
src/gallium/drivers/r600/radeon_video.h
View file

@ -65,7 +65,7 @@ bool rvid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs,
void rvid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer);
/* join surfaces into the same buffer with identical tiling params
sumup their sizes and replace the backend buffers with a single bo */
sum up their sizes and replace the backend buffers with a single bo */
void rvid_join_surfaces(struct r600_common_context *rctx,
struct pb_buffer** buffers[VL_NUM_COMPONENTS],
struct radeon_surf *surfaces[VL_NUM_COMPONENTS]);

2
src/gallium/drivers/r600/sb/sb_ir.h
View file

@ -930,7 +930,7 @@ public:
bool empty() { assert(first != NULL || first == last); return !first; }
unsigned count();
// used with node containers that represent shceduling queues
// used with node containers that represent scheduling queues
// ignores copies and takes into account alu_packed_node items
unsigned real_alu_count();

2
src/gallium/drivers/r600/sfn/sfn_alu_defines.h
View file

@ -32,7 +32,7 @@
namespace r600 {
/* ALU op2 instructions 17:7 top three bits alwayss zero. */
/* ALU op2 instructions 17:7 top three bits always zero. */
enum EAluOp {
op2_add = 0,
op2_mul = 1,

6
src/gallium/drivers/r600/sfn/sfn_conditionaljumptracker.cpp
View file

@ -181,13 +181,13 @@ void LoopFrame::fixup_mid(UNUSED r600_bytecode_cf *mid)
void LoopFrame::fixup_pop(r600_bytecode_cf *final)
{
/* LOOP END addess is past LOOP START */
/* LOOP END address is past LOOP START */
final->cf_addr = start->id + 2;
/* LOOP START addess is past LOOP END*/
/* LOOP START address is past LOOP END*/
start->cf_addr = final->id + 2;
/* BREAK amd CONINUE point at LOOP END*/
/* BREAK and CONTINUE point at LOOP END*/
for (auto m : mid)
m->cf_addr = final->id;
}

2
src/gallium/drivers/r600/sfn/sfn_debug.cpp
View file

@ -68,7 +68,7 @@ static const struct debug_named_value sfn_debug_options[] = {
{"ass", SfnLog::assembly, "Log IR to assembly conversion"},
{"flow", SfnLog::flow, "Log Flow instructions"},
{"merge", SfnLog::merge, "Log register merge operations"},
{"nomerge", SfnLog::nomerge, "Skup egister merge step"},
{"nomerge", SfnLog::nomerge, "Skip register merge step"},
{"tex", SfnLog::tex, "Log texture ops"},
{"trans", SfnLog::trans, "Log generic translation messages"},
DEBUG_NAMED_VALUE_END

2
src/gallium/drivers/r600/sfn/sfn_debug.h
View file

@ -34,7 +34,7 @@
#include "compiler/nir/nir.h"
namespace r600 {
/* Implemnt some logging for shader-from-nir
/* Implement some logging for shader-from-nir
*/

2
src/gallium/drivers/r600/sfn/sfn_defines.h
View file

@ -303,7 +303,7 @@ enum EVFetchFlagShift {
vtx_alt_const,
vtx_use_tc,
vtx_vpm,
vtx_unknwon
vtx_unknown
};
enum EBufferIndexMode {

6
src/gallium/drivers/r600/sfn/sfn_docu.txt
View file

@ -11,8 +11,8 @@ CTS gles
- 3 no regressions, a few fixes compared to TGSI
- 31
* a few fixes with interpolation specifiers
* a few regressiones with seperate_shader.random
* syncronization has some unstable tests, this might be because global syncronization is missing (in both)
* a few regressions with separate_shader.random
* synchronization has some unstable tests, this might be because global synchronization is missing (in both)
## Currently missing features w.r.t. TGSI:
@ -29,7 +29,7 @@ CTS gles
- copy propagation:
- Moves from inputs are usually not required, they could be forwarded
- texture operations often move additional parameters in extra registers
but they are actually needed in the same registes they come from and
but they are actually needed in the same registers they come from and
could just be swizzled into the right place
(lower in NIR like it is done in e.g. in ETNAVIV)

34
src/gallium/drivers/r600/sfn/sfn_emittexinstruction.cpp
View file

@ -157,7 +157,7 @@ bool EmitTexInstruction::emit_cube_txd(nir_tex_instr* instr, TexInputs& tex_src)
{alu_last_instr, alu_write}));
}
auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, tex_src.sampler_deref);
assert(!sampler.indirect);
TexInstruction *irgh = new TexInstruction(TexInstruction::set_gradient_h, empty_dst, tex_src.ddx,
@ -217,7 +217,7 @@ bool EmitTexInstruction::emit_cube_txl(nir_tex_instr* instr, TexInputs& tex_src)
GPRVector src(src_elms);
GPRVector dst(dst_elms);
auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, tex_src.sampler_deref);
assert(!sampler.indirect);
auto tir = new TexInstruction(TexInstruction::sample_l, dst, src,
@ -242,7 +242,7 @@ bool EmitTexInstruction::emit_cube_lod(nir_tex_instr* instr, TexInputs& src)
GPRVector cubed(v);
emit_cube_prep(src.coord, cubed, instr->is_array);
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect);
auto dst = make_dest(*instr);
@ -293,7 +293,7 @@ bool EmitTexInstruction::emit_cube_txb(nir_tex_instr* instr, TexInputs& tex_src)
tex_op = TexInstruction::sample_c_lb;
}
auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, tex_src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
auto tir = new TexInstruction(tex_op, dst, src,
@ -332,7 +332,7 @@ bool EmitTexInstruction::emit_cube_tex(nir_tex_instr* instr, TexInputs& tex_src)
GPRVector dst(dst_elms);
GPRVector src(src_elms);
auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, tex_src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
auto tir = new TexInstruction(tex_op, dst, src,
@ -411,7 +411,7 @@ bool EmitTexInstruction::emit_tex_tex(nir_tex_instr* instr, TexInputs& src)
auto tex_op = TexInstruction::sample;
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect);
if (instr->is_shadow) {
@ -450,7 +450,7 @@ bool EmitTexInstruction::emit_tex_txd(nir_tex_instr* instr, TexInputs& src)
tex_op = TexInstruction::sample_c_g;
}
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
TexInstruction *irgh = new TexInstruction(TexInstruction::set_gradient_h, empty_dst, src.ddx,
@ -491,7 +491,7 @@ bool EmitTexInstruction::emit_tex_txf(nir_tex_instr* instr, TexInputs& src)
src.coord.set_reg_i(3, src.lod);
}
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect);
/* txf doesn't need rounding for the array index, but 1D has the array index
@ -527,7 +527,7 @@ bool EmitTexInstruction::emit_tex_lod(nir_tex_instr* instr, TexInputs& src)
{
auto tex_op = TexInstruction::get_tex_lod;
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
auto dst = make_dest(*instr);
@ -560,7 +560,7 @@ bool EmitTexInstruction::emit_tex_txl(nir_tex_instr* instr, TexInputs& src)
else
src.coord.set_reg_i(3, src.lod);
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
auto dst = make_dest(*instr);
@ -598,7 +598,7 @@ bool EmitTexInstruction::emit_tex_txb(nir_tex_instr* instr, TexInputs& src)
GPRVector tex_src(src.coord, in_swizzle);
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
auto dst = make_dest(*instr);
@ -635,7 +635,7 @@ bool EmitTexInstruction::emit_tex_txs(nir_tex_instr* instr, TexInputs& tex_src,
src_elms[i] = tex_src.lod;
GPRVector src(src_elms);
auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, tex_src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
auto ir = new TexInstruction(TexInstruction::get_resinfo, dst, src,
@ -681,7 +681,7 @@ bool EmitTexInstruction::emit_tex_tg4(nir_tex_instr* instr, TexInputs& src)
tex_op = TexInstruction::gather4_c;
}
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
bool literal_offset = false;
@ -768,7 +768,7 @@ bool EmitTexInstruction::emit_cube_tg4(nir_tex_instr* instr, TexInputs& tex_src)
GPRVector dst(dst_elms);
GPRVector src(src_elms);
auto sampler = get_samplerr_id(instr->sampler_index, tex_src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, tex_src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
auto tir = new TexInstruction(tex_op, dst, src, sampler.id,
@ -793,7 +793,7 @@ bool EmitTexInstruction::emit_tex_txf_ms(nir_tex_instr* instr, TexInputs& src)
<< *reinterpret_cast<nir_instr*>(instr)
<< "' (" << __func__ << ")\n";
auto sampler = get_samplerr_id(instr->sampler_index, src.sampler_deref);
auto sampler = get_sampler_id(instr->sampler_index, src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
int sample_id = allocate_temp_register();
@ -802,7 +802,7 @@ bool EmitTexInstruction::emit_tex_txf_ms(nir_tex_instr* instr, TexInputs& src)
PValue help(new GPRValue(sample_id, 1));
/* FIXME: Texture destination registers must be handled differently,
* because the swizzle identfies which source componnet has to be written
* because the swizzle identifies which source component has to be written
* at a certain position, and the target register is actually different.
* At this point we just add a helper register, but for later work (scheduling
* and optimization on the r600 IR level, this needs to be implemented
@ -997,7 +997,7 @@ void EmitTexInstruction::handle_array_index(const nir_tex_instr& instr, const GP
}
EmitTexInstruction::SamplerId
EmitTexInstruction::get_samplerr_id(int sampler_id, const nir_variable *deref)
EmitTexInstruction::get_sampler_id(int sampler_id, const nir_variable *deref)
{
EmitTexInstruction::SamplerId result = {sampler_id, false};

2
src/gallium/drivers/r600/sfn/sfn_emittexinstruction.h
View file

@ -97,7 +97,7 @@ private:
bool indirect;
};
SamplerId get_samplerr_id(int sampler_id, const nir_variable *deref);
SamplerId get_sampler_id(int sampler_id, const nir_variable *deref);
};

4
src/gallium/drivers/r600/sfn/sfn_instruction_alu.cpp
View file

@ -112,9 +112,9 @@ bool AluInstruction::is_equal_to(const Instruction& lhs) const
return (m_flags == oth.m_flags && m_cf_type == oth.m_cf_type);
}
void AluInstruction::replace_values(const ValueSet& candiates, PValue new_value)
void AluInstruction::replace_values(const ValueSet& candidates, PValue new_value)
{
for (auto c: candiates) {
for (auto c: candidates) {
if (*c == *m_dest)
m_dest = new_value;

2
src/gallium/drivers/r600/sfn/sfn_instruction_alu.h
View file

@ -117,7 +117,7 @@ public:
ECFAluOpCode cf_type() const {return m_cf_type;}
void set_cf_type(ECFAluOpCode cf_type){ m_cf_type = cf_type; }
void replace_values(const ValueSet& candiates, PValue new_value) override;
void replace_values(const ValueSet& candidates, PValue new_value) override;
private:

2
src/gallium/drivers/r600/sfn/sfn_instruction_base.cpp
View file

@ -146,7 +146,7 @@ void Instruction::add_remappable_dst_value(GPRVector *v)
m_mappable_dst_vectors.push_back(v);
}
void Instruction::replace_values(UNUSED const ValueSet& candiates, UNUSED PValue new_value)
void Instruction::replace_values(UNUSED const ValueSet& candidates, UNUSED PValue new_value)
{
}

2
src/gallium/drivers/r600/sfn/sfn_instruction_base.h
View file

@ -108,7 +108,7 @@ public:
void print(std::ostream& os) const;
virtual void replace_values(const ValueSet& candiates, PValue new_value);
virtual void replace_values(const ValueSet& candidates, PValue new_value);
void evalue_liveness(LiverangeEvaluator& eval) const;

16
src/gallium/drivers/r600/sfn/sfn_instruction_export.cpp
View file

@ -38,18 +38,18 @@ WriteoutInstruction::WriteoutInstruction(instr_type t, const GPRVector& value):
add_remappable_src_value(&m_value);
}
void WriteoutInstruction::replace_values(const ValueSet& candiates, PValue new_value)
void WriteoutInstruction::replace_values(const ValueSet& candidates, PValue new_value)
{
// I wonder whether we can actually end up here ...
for (auto c: candiates) {
for (auto c: candidates) {
if (*c == *m_value.reg_i(c->chan()))
m_value.set_reg_i(c->chan(), new_value);
}
replace_values_child(candiates, new_value);
replace_values_child(candidates, new_value);
}
void WriteoutInstruction::replace_values_child(UNUSED const ValueSet& candiates,
void WriteoutInstruction::replace_values_child(UNUSED const ValueSet& candidates,
UNUSED PValue new_value)
{
}
@ -168,12 +168,12 @@ void WriteScratchInstruction::do_print(std::ostream& os) const
<< " " << gpr() << " AL:" << m_align << " ALO:" << m_align_offset;
}
void WriteScratchInstruction::replace_values_child(const ValueSet& candiates, PValue new_value)
void WriteScratchInstruction::replace_values_child(const ValueSet& candidates, PValue new_value)
{
if (!m_address)
return;
for (auto c: candiates) {
for (auto c: candidates) {
if (*c == *m_address)
m_address = new_value;
}
@ -304,13 +304,13 @@ void MemRingOutIntruction::do_print(std::ostream& os) const
}
void MemRingOutIntruction::replace_values_child(const ValueSet& candiates,
void MemRingOutIntruction::replace_values_child(const ValueSet& candidates,
PValue new_value)
{
if (!m_index)
return;
for (auto c: candiates) {
for (auto c: candidates) {
if (*c == *m_index)
m_index = new_value;
}

8
src/gallium/drivers/r600/sfn/sfn_instruction_export.h
View file

@ -33,13 +33,13 @@ namespace r600 {
class WriteoutInstruction: public Instruction {
public:
void replace_values(const ValueSet& candiates, PValue new_value) override;
void replace_values(const ValueSet& candidates, PValue new_value) override;
const GPRVector& gpr() const {return m_value;}
const GPRVector *gpr_ptr() const {return &m_value;}
protected:
WriteoutInstruction(instr_type t, const GPRVector& value);
private:
virtual void replace_values_child(const ValueSet& candiates, PValue new_value);
virtual void replace_values_child(const ValueSet& candidates, PValue new_value);
virtual void remap_registers_child(std::vector<rename_reg_pair>& map,
ValueMap& values);
@ -91,7 +91,7 @@ private:
bool is_equal_to(const Instruction& lhs) const override;
void do_print(std::ostream& os) const override;
void replace_values_child(const ValueSet& candiates, PValue new_value) override;
void replace_values_child(const ValueSet& candidates, PValue new_value) override;
void remap_registers_child(std::vector<rename_reg_pair>& map,
ValueMap& values)override;
@ -149,7 +149,7 @@ public:
EMemWriteType type() const {return m_type;}
unsigned index_reg() const {return m_index->sel();}
unsigned array_base() const {return m_base_address; }
void replace_values_child(const ValueSet& candiates, PValue new_value) override;
void replace_values_child(const ValueSet& candidates, PValue new_value) override;
void remap_registers_child(std::vector<rename_reg_pair>& map,
ValueMap& values) override;
void patch_ring(int stream, PValue index);

6
src/gallium/drivers/r600/sfn/sfn_instruction_fetch.cpp
View file

@ -231,11 +231,11 @@ FetchInstruction::FetchInstruction(GPRVector dst, PValue src, int scratch_size):
add_remappable_src_value(&m_buffer_offset);
}
void FetchInstruction::replace_values(const ValueSet& candiates, PValue new_value)
void FetchInstruction::replace_values(const ValueSet& candidates, PValue new_value)
{
if (!m_src)
return;
for (auto c: candiates) {
for (auto c: candidates) {
for (int i = 0; i < 4; ++i) {
if (*c == *m_dst.reg_i(i))
m_dst.set_reg_i(i, new_value);
@ -470,7 +470,7 @@ void FetchInstruction::do_print(std::ostream& os) const
if (m_flags.any()) {
os << " Flags:";
for( int i = 0; i < vtx_unknwon; ++i) {
for( int i = 0; i < vtx_unknown; ++i) {
if (m_flags.test(i))
os << ' ' << flag_string[i];
}

2
src/gallium/drivers/r600/sfn/sfn_instruction_fetch.h
View file

@ -78,7 +78,7 @@ public:
FetchInstruction(GPRVector dst, PValue src, int scratch_size);
void replace_values(const ValueSet& candiates, PValue new_value) override;
void replace_values(const ValueSet& candidates, PValue new_value) override;
EVFetchInstr vc_opcode() const { return m_vc_opcode;}
EVFetchType fetch_type() const { return m_fetch_type;}

4
src/gallium/drivers/r600/sfn/sfn_instruction_gds.cpp
View file

@ -155,9 +155,9 @@ GDSStoreTessFactor::GDSStoreTessFactor(GPRVector& value):
add_remappable_src_value(&m_value);
}
void GDSStoreTessFactor::replace_values(const ValueSet& candiates, PValue new_value)
void GDSStoreTessFactor::replace_values(const ValueSet& candidates, PValue new_value)
{
for (auto& c: candiates) {
for (auto& c: candidates) {
for (int i = 0; i < 4; ++i) {
if (*c == *m_value[i])
m_value[i] = new_value;

2
src/gallium/drivers/r600/sfn/sfn_instruction_gds.h
View file

@ -201,7 +201,7 @@ public:
int sel() const {return m_value.sel();}
int chan(int i ) const {return m_value.chan_i(i);}
void replace_values(const ValueSet& candiates, PValue new_value) override;
void replace_values(const ValueSet& candidates, PValue new_value) override;
private:
bool is_equal_to(const Instruction& lhs) const override;
void do_print(std::ostream& os) const override;

8
src/gallium/drivers/r600/sfn/sfn_instruction_lds.cpp
View file

@ -25,9 +25,9 @@ LDSReadInstruction::LDSReadInstruction(std::vector<PValue>& address, std::vector
}
}
void LDSReadInstruction::replace_values(const ValueSet& candiates, PValue new_value)
void LDSReadInstruction::replace_values(const ValueSet& candidates, PValue new_value)
{
for (auto& c : candiates) {
for (auto& c : candidates) {
for (auto& d: m_dest_value) {
if (*c == *d)
d = new_value;
@ -116,9 +116,9 @@ void LDSWriteInstruction::do_print(std::ostream& os) const
os << ", " << value1();
}
void LDSWriteInstruction::replace_values(const ValueSet& candiates, PValue new_value)
void LDSWriteInstruction::replace_values(const ValueSet& candidates, PValue new_value)
{
for (auto c: candiates) {
for (auto c: candidates) {
if (*c == *m_address)
m_address = new_value;

4
src/gallium/drivers/r600/sfn/sfn_instruction_lds.h
View file

@ -8,7 +8,7 @@ namespace r600 {
class LDSReadInstruction : public Instruction {
public:
LDSReadInstruction(std::vector<PValue>& value, std::vector<PValue>& address);
void replace_values(const ValueSet& candiates, PValue new_value) override;
void replace_values(const ValueSet& candidates, PValue new_value) override;
unsigned num_values() const { return m_dest_value.size();}
const Value& address(unsigned i) const { return *m_address[i];}
@ -54,7 +54,7 @@ public:
unsigned num_components() const { return m_value1 ? 2 : 1;}
unsigned idx_offset() const {return m_idx_offset;};
void replace_values(const ValueSet& candiates, PValue new_value) override;
void replace_values(const ValueSet& candidates, PValue new_value) override;
private:
void do_print(std::ostream& os) const override;

4
src/gallium/drivers/r600/sfn/sfn_instruction_tex.cpp
View file

@ -56,10 +56,10 @@ void TexInstruction::set_gather_comp(int cmp)
m_inst_mode = cmp;
}
void TexInstruction::replace_values(const ValueSet& candiates, PValue new_value)
void TexInstruction::replace_values(const ValueSet& candidates, PValue new_value)
{
// I wonder whether we can actually end up here ...
for (auto c: candiates) {
for (auto c: candidates) {
if (*c == *m_src.reg_i(c->chan()))
m_src.set_reg_i(c->chan(), new_value);
if (*c == *m_dst.reg_i(c->chan()))

2
src/gallium/drivers/r600/sfn/sfn_instruction_tex.h
View file

@ -81,7 +81,7 @@ public:
unsigned sampler_id() const {return m_sampler_id;}
unsigned resource_id() const {return m_resource_id;}
void replace_values(const ValueSet& candiates, PValue new_value) override;
void replace_values(const ValueSet& candidates, PValue new_value) override;
void set_offset(unsigned index, int32_t val);
int get_offset(unsigned index) const;

4
src/gallium/drivers/r600/sfn/sfn_ir_to_assembly.cpp
View file

@ -266,7 +266,7 @@ bool AssemblyFromShaderLegacyImpl::emit_alu(const AluInstruction& ai, ECFAluOpCo
++m_nliterals_in_group;
}
/* This instruction group would exeed the limit of literals, so
/* This instruction group would exceed the limit of literals, so
* force a new instruction group by adding a NOP as last
* instruction. This will no loner be needed with a real
* scheduler */
@ -967,7 +967,7 @@ bool AssemblyFromShaderLegacyImpl::emit_ldsread(const LDSReadInstruction& instr)
r600_bytecode_alu alu_read;
/* We must add a new ALU clause if the fetch and read op would be split otherwise
* r600_asm limites at 120 slots = 240 dwords */
* r600_asm limits at 120 slots = 240 dwords */
if (m_bc->cf_last->ndw > 240 - 4 * n_values)
m_bc->force_add_cf = 1;

2
src/gallium/drivers/r600/sfn/sfn_liverange.cpp
View file

@ -706,7 +706,7 @@ register_live_range temp_comp_access::get_required_live_range()
first_write_scope = first_write_scope->parent();
/* Propagte live_range if we are now in a loop */
/* Propagate live_range if we are now in a loop */
if (keep_for_full_loop && first_write_scope->is_loop())
propagate_live_range_to_dominant_write_scope();
}

8
src/gallium/drivers/r600/sfn/sfn_liverange.h
View file

@ -55,9 +55,9 @@ enum prog_scope_type {
loop_body, /* Inside a loop */
if_branch, /* Inside if branch */
else_branch, /* Inside else branch */
switch_body, /* Inside switch statmenet */
switch_case_branch, /* Inside switch case statmenet */
switch_default_branch, /* Inside switch default statmenet */
switch_body, /* Inside switch statement */
switch_case_branch, /* Inside switch case statement */
switch_default_branch, /* Inside switch default statement */
undefined_scope
};
@ -180,7 +180,7 @@ private:
static const int supported_ifelse_nesting_depth = 32;
/* Tracks the last if scope in which the temporary was written to
* without a write in the correspondig else branch. Is also used
* without a write in the corresponding else branch. Is also used
* to track read-before-write in the according scope.
*/
const prog_scope *current_unpaired_if_write_scope;

2
src/gallium/drivers/r600/sfn/sfn_shader_base.cpp
View file

@ -799,7 +799,7 @@ GPRVector ShaderFromNirProcessor::vec_from_nir_with_fetch_constant(const nir_src
std::array<bool,4> used_swizzles = {false, false, false, false};
/* Check whether all sources come from a GPR, and,
* if requested, whether they are swizzled as epected */
* if requested, whether they are swizzled as expected */
for (int i = 0; i < 4 && use_same; ++i) {
if ((1 << i) & mask) {

2
src/gallium/drivers/r600/sfn/sfn_shader_fragment.cpp
View file

@ -68,7 +68,7 @@ bool FragmentShaderFromNir::do_process_inputs(nir_variable *input)
bool FragmentShaderFromNir::do_emit_load_deref(const nir_variable *in_var, nir_intrinsic_instr* instr)
{
assert(0 && "all input derefs should have benn lowered");
assert(0 && "all input derefs should have been lowered");
return false;
}