mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-07 17:58:26 +02:00
nv50: re-add proper TEXBIAS sequence
This commit is contained in:
Christoph Bumiller
parent
07fe7c2f02
commit
6f9978050e
7 changed files with 265 additions and 74 deletions
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@ -204,6 +204,35 @@ nvcg_replace_value(struct nv_pc *pc, struct nv_value *old_val,
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return n;
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}
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struct nv_value *
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nvcg_find_constant(struct nv_ref *ref)
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{
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struct nv_value *src;
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if (!ref)
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return NULL;
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src = ref->value;
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while (src->insn && src->insn->opcode == NV_OP_MOV) {
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assert(!src->insn->src[0]->mod);
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src = src->insn->src[0]->value;
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}
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if ((src->reg.file == NV_FILE_IMM) ||
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(src->insn && src->insn->opcode == NV_OP_LDA &&
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src->insn->src[0]->value->reg.file >= NV_FILE_MEM_C(0) &&
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src->insn->src[0]->value->reg.file <= NV_FILE_MEM_C(15)))
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return src;
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return NULL;
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}
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struct nv_value *
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nvcg_find_immediate(struct nv_ref *ref)
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{
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struct nv_value *src = nvcg_find_constant(ref);
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return (src && src->reg.file == NV_FILE_IMM) ? src : NULL;
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}
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static void
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nv_pc_free_refs(struct nv_pc *pc)
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{
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@ -126,6 +126,7 @@
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#define NV_TYPE_ISINT(t) ((t) <= 5)
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#define NV_TYPE_ISFLT(t) ((t) & 0x08)
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/* $cX registers contain 4 bits: OCSZ (Z is bit 0) */
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#define NV_CC_FL 0x0
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#define NV_CC_LT 0x1
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#define NV_CC_EQ 0x2
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@ -135,6 +136,10 @@
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#define NV_CC_GE 0x6
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#define NV_CC_U 0x8
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#define NV_CC_TR 0xf
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#define NV_CC_O 0x10
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#define NV_CC_C 0x11
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#define NV_CC_A 0x12
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#define NV_CC_S 0x13
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#define NV_PC_MAX_INSTRUCTIONS 2048
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#define NV_PC_MAX_VALUES (NV_PC_MAX_INSTRUCTIONS * 4)
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@ -241,7 +246,7 @@ struct nv_instruction {
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ubyte saturate : 1;
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ubyte centroid : 1;
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ubyte flat : 1;
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ubyte padding : 4;
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ubyte lanes : 4;
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ubyte tex_live : 1;
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/* */
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ubyte tex_t; /* TIC binding */
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@ -459,6 +464,8 @@ boolean nvbb_reachable_by(struct nv_basic_block *, struct nv_basic_block *,
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struct nv_basic_block *nvbb_dom_frontier(struct nv_basic_block *);
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int nvcg_replace_value(struct nv_pc *pc, struct nv_value *old_val,
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struct nv_value *new_val);
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struct nv_value *nvcg_find_immediate(struct nv_ref *);
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struct nv_value *nvcg_find_constant(struct nv_ref *);
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typedef void (*nv_pc_pass_func)(void *priv, struct nv_basic_block *b);
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@ -540,8 +540,9 @@ emit_mov(struct nv_pc *pc, struct nv_instruction *i)
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set_a16_bits(pc, SREG(i->src[0])->id);
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} else
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if (DFILE(i, 0) == NV_FILE_FLAGS) {
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pc->emit[0] = 0x000001fd;
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pc->emit[1] = 0xa0000788 | (1 << 6);
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pc->emit[0] = 0x00000001;
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pc->emit[1] = 0xa0000000 | (1 << 6);
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set_pred(pc, i);
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pc->emit[0] |= SREG(i->src[0])->id << 9;
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pc->emit[1] |= DREG(i->def[0])->id << 4;
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} else
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@ -984,7 +985,7 @@ emit_tex(struct nv_pc *pc, struct nv_instruction *i)
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pc->emit[0] |= i->tex_t << 9;
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pc->emit[0] |= i->tex_s << 17;
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pc->emit[0] |= i->tex_argc << 22;
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pc->emit[0] |= (i->tex_argc - 1) << 22;
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pc->emit[0] |= (i->tex_mask & 0x3) << 25;
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pc->emit[1] |= (i->tex_mask & 0xc) << 12;
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@ -1000,8 +1001,6 @@ emit_tex(struct nv_pc *pc, struct nv_instruction *i)
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else
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if (i->opcode == NV_OP_TXL)
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pc->emit[1] |= 0x40000000;
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else
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pc->emit[0] -= 1 << 22;
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}
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static void
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@ -1053,6 +1052,20 @@ emit_ddy(struct nv_pc *pc, struct nv_instruction *i)
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set_pred_wr(pc, i);
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}
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static void
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emit_quadop(struct nv_pc *pc, struct nv_instruction *i)
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{
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pc->emit[0] = 0xc0000000;
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pc->emit[1] = 0x80000000;
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emit_form_ADD(pc, i);
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pc->emit[0] |= i->lanes << 16;
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pc->emit[0] |= (i->quadop & 0x03) << 20;
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pc->emit[1] |= (i->quadop & 0xfc) << 20;
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}
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void
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nv50_emit_instruction(struct nv_pc *pc, struct nv_instruction *i)
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{
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@ -1132,6 +1145,9 @@ nv50_emit_instruction(struct nv_pc *pc, struct nv_instruction *i)
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case NV_OP_TXL:
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emit_tex(pc, i);
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break;
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case NV_OP_QUADOP:
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emit_quadop(pc, i);
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break;
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case NV_OP_KIL:
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emit_flow(pc, i, 0x0);
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break;
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@ -1162,7 +1178,7 @@ nv50_emit_instruction(struct nv_pc *pc, struct nv_instruction *i)
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case NV_OP_UNDEF:
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case NV_OP_SUB:
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NOUVEAU_ERR("operation \"%s\" should have been eliminated\n",
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nv_opcode_name(i->opcode));
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nv_opcode_name(i->opcode));
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break;
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default:
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NOUVEAU_ERR("unhandled NV_OP: %d\n", i->opcode);
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@ -94,14 +94,17 @@ nvi_isnop(struct nv_instruction *nvi)
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if (nvi->opcode == NV_OP_EXPORT || nvi->opcode == NV_OP_UNDEF)
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return TRUE;
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if (nvi->fixed ||
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nvi->is_terminator ||
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nvi->flags_src ||
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/* NOTE: 'fixed' now only means that it shouldn't be optimized away,
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* but we can still remove it if it is a no-op move.
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*/
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if (/* nvi->fixed || */
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/* nvi->flags_src || */ /* cond. MOV to same register is still NOP */
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nvi->flags_def ||
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nvi->is_terminator ||
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nvi->is_join)
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return FALSE;
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if (nvi->def[0]->join->reg.id < 0)
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if (nvi->def[0] && nvi->def[0]->join->reg.id < 0)
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return TRUE;
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if (nvi->opcode != NV_OP_MOV && nvi->opcode != NV_OP_SELECT)
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@ -436,22 +439,6 @@ nv_pass_lower_mods(struct nv_pass *ctx, struct nv_basic_block *b)
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#define SRC_IS_MUL(s) ((s)->insn && (s)->insn->opcode == NV_OP_MUL)
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static struct nv_value *
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find_immediate(struct nv_ref *ref)
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{
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struct nv_value *src;
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if (!ref)
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return NULL;
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src = ref->value;
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while (src->insn && src->insn->opcode == NV_OP_MOV) {
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assert(!src->insn->src[0]->mod);
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src = src->insn->src[0]->value;
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}
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return (src->reg.file == NV_FILE_IMM) ? src : NULL;
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}
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static void
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modifiers_apply(uint32_t *val, ubyte type, ubyte mod)
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{
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@ -663,8 +650,8 @@ nv_pass_lower_arith(struct nv_pass *ctx, struct nv_basic_block *b)
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next = nvi->next;
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src0 = find_immediate(nvi->src[0]);
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src1 = find_immediate(nvi->src[1]);
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src0 = nvcg_find_immediate(nvi->src[0]);
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src1 = nvcg_find_immediate(nvi->src[1]);
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if (src0 && src1)
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constant_expression(ctx->pc, nvi, src0, src1);
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@ -778,6 +765,7 @@ nv_pass_reload_elim(struct nv_pass_reld_elim *ctx, struct nv_basic_block *b)
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if (ld->def[0]->reg.id >= 0)
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it->value = ld->def[0];
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else
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if (!ld->fixed)
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nvcg_replace_value(ctx->pc, ld->def[0], it->value);
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} else {
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if (ctx->alloc == LOAD_RECORD_POOL_SIZE)
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@ -979,7 +967,7 @@ nv_pass_cse(struct nv_pass *ctx, struct nv_basic_block *b)
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for (ir = entry; ir; ir = next) {
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next = ir->next;
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for (ik = entry; ik != ir; ik = ik->next) {
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if (ir->opcode != ik->opcode)
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if (ir->opcode != ik->opcode || ir->fixed)
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continue;
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if (!ir->def[0] || !ik->def[0] ||
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@ -102,7 +102,8 @@ static const char *nv_opcode_names[NV_OP_COUNT + 1] = {
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static const char *nv_cond_names[] =
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{
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"never", "lt" , "eq" , "le" , "gt" , "ne" , "ge" , "",
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"never", "ltu", "equ", "leu", "gtu", "neu", "geu", ""
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"never", "ltu", "equ", "leu", "gtu", "neu", "geu", "",
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"o", "c", "a", "s"
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};
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static const char *nv_modifier_strings[] =
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@ -144,7 +145,7 @@ nv_type_name(ubyte type)
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static INLINE const char *
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nv_cond_name(ubyte cc)
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{
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return nv_cond_names[MIN2(cc, 15)];
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return nv_cond_names[MIN2(cc, 19)];
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}
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static INLINE const char *
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@ -493,10 +493,10 @@ pass_join_values(struct nv_pc_pass *ctx, int iter)
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case NV_OP_SELECT:
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if (!iter)
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break;
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assert(join_allowed(ctx, i->def[0], i->src[0]->value));
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assert(join_allowed(ctx, i->def[0], i->src[1]->value));
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do_join_values(ctx, i->def[0], i->src[0]->value);
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do_join_values(ctx, i->def[0], i->src[1]->value);
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for (c = 0; c < 4 && i->src[c]; ++c) {
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assert(join_allowed(ctx, i->def[0], i->src[c]->value));
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do_join_values(ctx, i->def[0], i->src[c]->value);
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}
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break;
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case NV_OP_TEX:
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case NV_OP_TXB:
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@ -1156,8 +1156,8 @@ get_tex_dim(const struct tgsi_full_instruction *insn, int *dim, int *arg)
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static void
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load_proj_tex_coords(struct bld_context *bld,
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struct nv_value *t[4], int dim,
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const struct tgsi_full_instruction *insn)
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struct nv_value *t[4], int dim,
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const struct tgsi_full_instruction *insn)
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{
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int c, mask = 0;
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@ -1188,59 +1188,209 @@ load_proj_tex_coords(struct bld_context *bld,
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}
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}
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static void
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bld_tex(struct bld_context *bld, struct nv_value *dst0[4],
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const struct tgsi_full_instruction *insn)
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/* For a quad of threads / top left, top right, bottom left, bottom right
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* pixels, do a different operation, and take src0 from a specific thread.
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*/
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#define QOP_ADD 0
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#define QOP_SUBR 1
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#define QOP_SUB 2
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#define QOP_MOV1 3
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#define QOP(a, b, c, d) \
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((QOP_##a << 0) | (QOP_##b << 2) | (QOP_##c << 4) | (QOP_##d << 6))
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static INLINE struct nv_value *
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bld_quadop(struct bld_context *bld, ubyte qop, struct nv_value *src0, int lane,
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struct nv_value *src1, boolean wp)
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{
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struct nv_value *val = bld_insn_2(bld, NV_OP_QUADOP, src0, src1);
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val->insn->lanes = lane;
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val->insn->quadop = qop;
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if (wp) {
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val->insn->flags_def = new_value(bld->pc, NV_FILE_FLAGS, NV_TYPE_U16);
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val->insn->flags_def->insn = val->insn;
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}
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return val;
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}
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static INLINE struct nv_value *
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bld_cmov(struct bld_context *bld,
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struct nv_value *src, ubyte cc, struct nv_value *cr)
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{
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src = bld_insn_1(bld, NV_OP_MOV, src);
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src->insn->cc = cc;
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src->insn->flags_src = new_ref(bld->pc, cr);
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return src;
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}
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static struct nv_instruction *
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emit_tex(struct bld_context *bld, uint opcode,
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struct nv_value *dst[4], struct nv_value *t_in[4],
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int argc, int tic, int tsc, int cube)
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{
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struct nv_value *t[4];
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struct nv_instruction *nvi;
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uint opcode = translate_opcode(insn->Instruction.Opcode);
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int arg, dim, c;
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int c;
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get_tex_dim(insn, &dim, &arg);
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if (insn->Texture.Texture == TGSI_TEXTURE_CUBE) {
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}
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// else
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if (insn->Instruction.Opcode == TGSI_OPCODE_TXP) {
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load_proj_tex_coords(bld, t, dim, insn);
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} else
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for (c = 0; c < dim; ++c)
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t[c] = emit_fetch(bld, insn, 0, c);
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if (arg != dim)
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t[dim] = emit_fetch(bld, insn, 0, 2);
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if (insn->Instruction.Opcode == TGSI_OPCODE_TXB ||
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insn->Instruction.Opcode == TGSI_OPCODE_TXL) {
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t[arg++] = emit_fetch(bld, insn, 0, 3);
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}
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for (c = 0; c < arg; ++c) {
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t[c] = bld_insn_1(bld, NV_OP_MOV, t[c]);
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/* the inputs to a tex instruction must be separate values */
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for (c = 0; c < argc; ++c) {
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t[c] = bld_insn_1(bld, NV_OP_MOV, t_in[c]);
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t[c]->reg.type = NV_TYPE_F32;
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t[c]->insn->fixed = 1;
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}
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nvi = new_instruction(bld->pc, opcode);
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for (c = 0; c < 4; ++c) {
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nvi->def[c] = dst0[c] = new_value(bld->pc, NV_FILE_GPR, NV_TYPE_F32);
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nvi->def[c]->insn = nvi;
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}
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for (c = 0; c < arg; ++c)
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for (c = 0; c < 4; ++c)
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dst[c] = bld_def(nvi, c, new_value(bld->pc, NV_FILE_GPR, NV_TYPE_F32));
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for (c = 0; c < argc; ++c)
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nvi->src[c] = new_ref(bld->pc, t[c]);
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nvi->tex_t = insn->Src[1].Register.Index;
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nvi->tex_s = 0;
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nvi->tex_t = tic;
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nvi->tex_s = tsc;
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nvi->tex_mask = 0xf;
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nvi->tex_cube = (insn->Texture.Texture == TGSI_TEXTURE_CUBE) ? 1 : 0;
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nvi->tex_cube = cube;
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nvi->tex_live = 0;
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nvi->tex_argc = arg;
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nvi->tex_argc = argc;
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return nvi;
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}
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static void
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bld_texlod_sequence(struct bld_context *bld,
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struct nv_value *dst[4], struct nv_value *t[4], int arg,
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int tic, int tsc, int cube)
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{
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emit_tex(bld, NV_OP_TXL, dst, t, arg, tic, tsc, cube); /* TODO */
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}
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/* The lanes of a quad are grouped by the bit in the condition register
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* they have set, which is selected by differing bias values.
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* Move the input values for TEX into a new register set for each group
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* and execute TEX only for a specific group.
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* We always need to use 4 new registers for the inputs/outputs because
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* the implicitly calculated derivatives must be correct.
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*/
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static void
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bld_texbias_sequence(struct bld_context *bld,
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struct nv_value *dst[4], struct nv_value *t[4], int arg,
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int tic, int tsc, int cube)
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{
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struct nv_instruction *sel, *tex;
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struct nv_value *bit[4], *cr[4], *res[4][4], *val;
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int l, c;
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const ubyte cc[4] = { NV_CC_EQ, NV_CC_S, NV_CC_C, NV_CC_O };
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for (l = 0; l < 4; ++l) {
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bit[l] = bld_load_imm_u32(bld, 1 << l);
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val = bld_quadop(bld, QOP(SUBR, SUBR, SUBR, SUBR),
|
||||
t[arg - 1], l, t[arg - 1], TRUE);
|
||||
|
||||
cr[l] = bld_cmov(bld, bit[l], NV_CC_EQ, val->insn->flags_def);
|
||||
|
||||
cr[l]->reg.file = NV_FILE_FLAGS;
|
||||
cr[l]->reg.type = NV_TYPE_U16;
|
||||
}
|
||||
|
||||
sel = new_instruction(bld->pc, NV_OP_SELECT);
|
||||
|
||||
for (l = 0; l < 4; ++l)
|
||||
sel->src[l] = new_ref(bld->pc, cr[l]);
|
||||
|
||||
bld_def(sel, 0, new_value(bld->pc, NV_FILE_FLAGS, NV_TYPE_U16));
|
||||
|
||||
for (l = 0; l < 4; ++l) {
|
||||
tex = emit_tex(bld, NV_OP_TXB, dst, t, arg, tic, tsc, cube);
|
||||
|
||||
tex->cc = cc[l];
|
||||
tex->flags_src = new_ref(bld->pc, sel->def[0]);
|
||||
|
||||
for (c = 0; c < 4; ++c)
|
||||
res[l][c] = tex->def[c];
|
||||
}
|
||||
|
||||
for (l = 0; l < 4; ++l)
|
||||
for (c = 0; c < 4; ++c)
|
||||
res[l][c] = bld_cmov(bld, res[l][c], cc[l], sel->def[0]);
|
||||
|
||||
for (c = 0; c < 4; ++c) {
|
||||
sel = new_instruction(bld->pc, NV_OP_SELECT);
|
||||
|
||||
for (l = 0; l < 4; ++l)
|
||||
sel->src[l] = new_ref(bld->pc, res[l][c]);
|
||||
|
||||
bld_def(sel, 0, (dst[c] = new_value(bld->pc, NV_FILE_GPR, NV_TYPE_F32)));
|
||||
}
|
||||
}
|
||||
|
||||
static boolean
|
||||
bld_is_constant(struct nv_value *val)
|
||||
{
|
||||
if (val->reg.file == NV_FILE_IMM)
|
||||
return TRUE;
|
||||
return val->insn && nvcg_find_constant(val->insn->src[0]);
|
||||
}
|
||||
|
||||
static void
|
||||
bld_tex(struct bld_context *bld, struct nv_value *dst0[4],
|
||||
const struct tgsi_full_instruction *insn)
|
||||
{
|
||||
struct nv_value *t[4], *s[3];
|
||||
uint opcode = translate_opcode(insn->Instruction.Opcode);
|
||||
int arg, dim, c;
|
||||
const int tic = insn->Src[1].Register.Index;
|
||||
const int tsc = 0;
|
||||
const int cube = (insn->Texture.Texture == TGSI_TEXTURE_CUBE) ? 1 : 0;
|
||||
|
||||
get_tex_dim(insn, &dim, &arg);
|
||||
|
||||
if (!cube && insn->Instruction.Opcode == TGSI_OPCODE_TXP)
|
||||
load_proj_tex_coords(bld, t, dim, insn);
|
||||
else
|
||||
for (c = 0; c < dim; ++c)
|
||||
t[c] = emit_fetch(bld, insn, 0, c);
|
||||
|
||||
if (cube) {
|
||||
assert(dim >= 3);
|
||||
for (c = 0; c < 3; ++c)
|
||||
s[c] = bld_insn_1(bld, NV_OP_ABS, t[c]);
|
||||
|
||||
s[0] = bld_insn_2(bld, NV_OP_MAX, s[0], s[1]);
|
||||
s[0] = bld_insn_2(bld, NV_OP_MAX, s[0], s[2]);
|
||||
s[0] = bld_insn_1(bld, NV_OP_RCP, s[0]);
|
||||
|
||||
for (c = 0; c < 3; ++c)
|
||||
t[c] = bld_insn_2(bld, NV_OP_MUL, t[c], s[0]);
|
||||
}
|
||||
|
||||
if (arg != dim)
|
||||
t[dim] = emit_fetch(bld, insn, 0, 2);
|
||||
|
||||
if (opcode == NV_OP_TXB || opcode == NV_OP_TXL) {
|
||||
t[arg++] = emit_fetch(bld, insn, 0, 3);
|
||||
|
||||
if ((bld->ti->p->type == PIPE_SHADER_FRAGMENT) &&
|
||||
!bld_is_constant(t[arg - 1])) {
|
||||
if (opcode == NV_OP_TXB)
|
||||
bld_texbias_sequence(bld, dst0, t, arg, tic, tsc, cube);
|
||||
else
|
||||
bld_texlod_sequence(bld, dst0, t, arg, tic, tsc, cube);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
emit_tex(bld, opcode, dst0, t, arg, tic, tsc, cube);
|
||||
}
|
||||
|
||||
static INLINE struct nv_value *
|
||||
bld_dot(struct bld_context *bld, const struct tgsi_full_instruction *insn,
|
||||
int n)
|
||||
int n)
|
||||
{
|
||||
struct nv_value *dotp, *src0, *src1;
|
||||
int c;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue