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radeonsi: remove the DRAW_PREAMBLE packet

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According to firmware guys, the new sequence that we added for Polaris should
work on all CIK parts, and should actually be faster on some parts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle 2016-07-14 16:21:52 +02:00
parent b89d0df535
commit 6f73c7595f
3 changed files with 1 additions and 12 deletions
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5
src/gallium/drivers/radeonsi/si_debug.c
View file

@ -286,11 +286,6 @@ static uint32_t *si_parse_packet3(FILE *f, uint32_t *ib, int *num_dw,
case PKT3_SET_SH_REG: case PKT3_SET_SH_REG:
si_parse_set_reg_packet(f, ib, count, SI_SH_REG_OFFSET); si_parse_set_reg_packet(f, ib, count, SI_SH_REG_OFFSET);
break; break;
case PKT3_DRAW_PREAMBLE:
si_dump_reg(f, R_030908_VGT_PRIMITIVE_TYPE, ib[1], ~0);
si_dump_reg(f, R_028AA8_IA_MULTI_VGT_PARAM, ib[2], ~0);
si_dump_reg(f, R_028B58_VGT_LS_HS_CONFIG, ib[3], ~0);
break;
case PKT3_ACQUIRE_MEM: case PKT3_ACQUIRE_MEM:
si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0); si_dump_reg(f, R_0301F0_CP_COHER_CNTL, ib[1], ~0);
si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0); si_dump_reg(f, R_0301F4_CP_COHER_SIZE, ib[2], ~0);

7
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -478,15 +478,10 @@ static void si_emit_draw_registers(struct si_context *sctx,
if (prim != sctx->last_prim || if (prim != sctx->last_prim ||
ia_multi_vgt_param != sctx->last_multi_vgt_param || ia_multi_vgt_param != sctx->last_multi_vgt_param ||
ls_hs_config != sctx->last_ls_hs_config) { ls_hs_config != sctx->last_ls_hs_config) {
if (sctx->b.family >= CHIP_POLARIS10) { if (sctx->b.chip_class >= CIK) {
radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param); radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config); radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config);
radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim); radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
} else if (sctx->b.chip_class >= CIK) {
radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
} else { } else {
radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim); radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);

1
src/gallium/drivers/radeonsi/sid.h
View file

@ -101,7 +101,6 @@
#define PKT3_INDIRECT_BUFFER_CONST 0x33 #define PKT3_INDIRECT_BUFFER_CONST 0x33
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34
#define PKT3_DRAW_INDEX_OFFSET_2 0x35 #define PKT3_DRAW_INDEX_OFFSET_2 0x35
#define PKT3_DRAW_PREAMBLE 0x36 /* new on CIK, required on GFX7.2 and later */
#define PKT3_WRITE_DATA 0x37 #define PKT3_WRITE_DATA 0x37
#define R_370_CONTROL 0x370 /* 0x[packet number][word index] */ #define R_370_CONTROL 0x370 /* 0x[packet number][word index] */
#define S_370_ENGINE_SEL(x) (((unsigned)(x) & 0x3) << 30) #define S_370_ENGINE_SEL(x) (((unsigned)(x) & 0x3) << 30)