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i965: Create a macro for setting all dirty bits.

Browse source 
This will make it easier to extend dirty bit handling to support
compute shaders.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Paul Berry 2014-01-10 14:23:52 -08:00 • committed by Jordan Justen
parent 88e3d404da
commit 6f56e1424d
4 changed files with 18 additions and 7 deletions
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4
src/mesa/drivers/dri/i965/brw_blorp.cpp
View file

@ -273,8 +273,8 @@ retry:
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
brw->state.dirty.brw = ~0;
brw->state.dirty.cache = ~0;
SET_DIRTY_ALL(brw);
SET_DIRTY_ALL(cache);
brw->no_depth_or_stencil = false;
brw->ib.type = -1;

11
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -248,6 +248,17 @@ struct brw_state_flags {
#define SET_DIRTY_BIT(FIELD, FLAG) brw->state.dirty.FIELD |= (FLAG)
/**
* Set all of the bits in a field of brw_state_flags.
*/
#define SET_DIRTY_ALL(FIELD) \
do { \
/* ~0 == 0xffffffff, so make sure field is <= 32 bits */ \
STATIC_ASSERT(sizeof(brw->state.dirty.FIELD) == 4); \
brw->state.dirty.FIELD = ~0; \
} while (false)
/** Subclass of Mesa vertex program */
struct brw_vertex_program {
struct gl_vertex_program program;

6
src/mesa/drivers/dri/i965/brw_state_cache.c
View file

@ -379,9 +379,9 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache *cache)
/* We need to make sure that the programs get regenerated, since
* any offsets leftover in brw_context will no longer be valid.
*/
brw->state.dirty.mesa |= ~0;
brw->state.dirty.brw |= ~0;
brw->state.dirty.cache |= ~0;
SET_DIRTY_ALL(mesa);
SET_DIRTY_ALL(brw);
SET_DIRTY_ALL(cache);
intel_batchbuffer_flush(brw);
}

4
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -383,8 +383,8 @@ void brw_init_state( struct brw_context *brw )
brw_upload_initial_gpu_state(brw);
brw->state.dirty.mesa = ~0;
brw->state.dirty.brw = ~0;
SET_DIRTY_ALL(mesa);
SET_DIRTY_ALL(brw);
/* Make sure that brw->state.dirty.brw has enough bits to hold all possible
* dirty flags.