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r600: fix cs atomic operations when the shader is called multiple times
This change is useful when the compute shader is called multiple
times with the atomic operations enabled. It fixes some data
coherency issues. This is done by moving
evergreen_emit_atomic_buffer_setup() after r600_flush_emit().
This change is also a partial fix for compute_shader.pipeline-compute-chain.
In this specific case, it makes the memory barrier working.
This change was tested on cayman and barts; it makes these tests
fully deterministic:
khr-gl4[2-6]/shader_atomic_counters/advanced-usage-many-dispatches: fail pass
khr-gles31/core/shader_atomic_counters/advanced-usage-many-dispatches: fail pass
deqp-gles31/functional/synchronization/inter_call/without_memory_barrier/atomic_counter_dispatch_.*_calls_.*_invocations: fail pass
Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
(cherry picked from commit dad942b468)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40359>
This commit is contained in:
parent
b1775f660a
commit
6f28830365
4 changed files with 7 additions and 9 deletions
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@ -4424,7 +4424,7 @@
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"description": "r600: fix cs atomic operations when the shader is called multiple times",
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"nominated": true,
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"nomination_type": 1,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": null,
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"notes": null
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@ -15,7 +15,6 @@ KHR-GLES31.core.gpu_shader5.texture_gather_offset_color_clamp_to_edge,Fail
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KHR-GLES31.core.layout_binding.image2D_layout_binding_imageLoad_ComputeShader,Fail
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KHR-GLES31.core.shader_atomic_counters.advanced-usage-many-dispatches,Fail
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KHR-GLES31.core.shader_atomic_counters.advanced-usage-many-draw-calls2,Fail
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KHR-GLES31.core.shader_atomic_counters.advanced-usage-multi-stage,Fail
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@ -1,6 +1,5 @@
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# Sometimes passes.
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KHR-GLES31.core.compute_shader.pipeline-compute-chain
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KHR-GLES31.core.shader_atomic_counters.advanced-usage-many-dispatches
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KHR-GLES31.core.shader_atomic_counters.advanced-usage-many-draw-calls2
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# Occasional "args_equal: Assertion `l.size() == r.size()' failed."
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@ -350,12 +350,6 @@ static void compute_emit_cs(struct r600_context *rctx,
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}
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r600_update_driver_const_buffers(rctx, true);
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evergreen_emit_atomic_buffer_setup(rctx, true, combined_atomics, global_atomic_count);
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if (global_atomic_count) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
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}
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/* Initialize all the compute-related registers.
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*
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* See evergreen_init_atom_start_compute_cs() in this file for the list
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@ -375,6 +369,12 @@ static void compute_emit_cs(struct r600_context *rctx,
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rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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r600_flush_emit(rctx);
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evergreen_emit_atomic_buffer_setup(rctx, true, combined_atomics, global_atomic_count);
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if (global_atomic_count) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
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}
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uint32_t rat_mask;
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rat_mask = evergreen_construct_rat_mask(rctx, &rctx->cb_misc_state, 0);
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