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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-04 09:10:12 +01:00
r600g: handle NULL colorbuffers correctly on R600-R700
This commit is contained in:
Marek Olšák
parent
07032d4068
commit
6e98a17551
1 changed files with 55 additions and 65 deletions
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@ -1558,12 +1558,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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if (rctx->framebuffer.state.nr_cbufs) {
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rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB;
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if (rctx->b.chip_class >= R700 &&
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rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
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rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
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}
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rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
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R600_CONTEXT_FLUSH_AND_INV_CB_META;
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}
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if (rctx->framebuffer.state.zsbuf) {
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rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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@ -1579,19 +1575,14 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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util_copy_framebuffer_state(&rctx->framebuffer.state, state);
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rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
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rctx->framebuffer.cb0_is_integer = state->nr_cbufs &&
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rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
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util_format_is_pure_integer(state->cbufs[0]->format);
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rctx->framebuffer.compressed_cb_mask = 0;
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rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
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state->cbufs[0] && state->cbufs[1] &&
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state->cbufs[0]->texture->nr_samples > 1 &&
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state->cbufs[1]->texture->nr_samples <= 1;
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if (state->nr_cbufs)
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rctx->framebuffer.nr_samples = state->cbufs[0]->texture->nr_samples;
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else if (state->zsbuf)
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rctx->framebuffer.nr_samples = state->zsbuf->texture->nr_samples;
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else
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rctx->framebuffer.nr_samples = 0;
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rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
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/* Colorbuffers. */
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for (i = 0; i < state->nr_cbufs; i++) {
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@ -1601,6 +1592,9 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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i == 1;
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surf = (struct r600_surface*)state->cbufs[i];
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if (!surf)
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continue;
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rtex = (struct r600_texture*)surf->base.texture;
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r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
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@ -1624,9 +1618,15 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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/* Update alpha-test state dependencies.
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* Alpha-test is done on the first colorbuffer only. */
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if (state->nr_cbufs) {
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bool alphatest_bypass = false;
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surf = (struct r600_surface*)state->cbufs[0];
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if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
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rctx->alphatest_state.bypass = surf->alphatest_bypass;
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if (surf) {
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alphatest_bypass = surf->alphatest_bypass;
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}
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if (rctx->alphatest_state.bypass != alphatest_bypass) {
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rctx->alphatest_state.bypass = alphatest_bypass;
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rctx->alphatest_state.atom.dirty = true;
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}
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}
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@ -1674,12 +1674,11 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
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10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/;
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if (rctx->framebuffer.state.nr_cbufs) {
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rctx->framebuffer.atom.num_dw += 6 * (2 + rctx->framebuffer.state.nr_cbufs);
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rctx->framebuffer.atom.num_dw += 6 * rctx->framebuffer.state.nr_cbufs; /* relocs */
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rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
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rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
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}
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if (rctx->framebuffer.state.zsbuf) {
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rctx->framebuffer.atom.num_dw += 18;
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rctx->framebuffer.atom.num_dw += 16;
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} else if (rctx->screen->b.info.drm_minor >= 18) {
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rctx->framebuffer.atom.num_dw += 3;
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}
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@ -1831,10 +1830,10 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
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/* Colorbuffers. */
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r600_write_context_reg_seq(cs, R_0280A0_CB_COLOR0_INFO, 8);
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for (i = 0; i < nr_cbufs; i++) {
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radeon_emit(cs, cb[i]->cb_color_info);
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radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0);
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}
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/* set CB_COLOR1_INFO for possible dual-src blending */
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if (i == 1) {
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if (i == 1 && cb[0]) {
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radeon_emit(cs, cb[0]->cb_color_info);
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i++;
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}
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@ -1843,65 +1842,56 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a
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}
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if (nr_cbufs) {
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/* COLOR_BASE */
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r600_write_context_reg_seq(cs, R_028040_CB_COLOR0_BASE, nr_cbufs);
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for (i = 0; i < nr_cbufs; i++) {
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radeon_emit(cs, cb[i]->cb_color_base);
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}
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unsigned reloc;
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/* relocations */
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for (i = 0; i < nr_cbufs; i++) {
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unsigned reloc = r600_context_bo_reloc(&rctx->b,
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&rctx->b.rings.gfx,
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(struct r600_resource*)cb[i]->base.texture,
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RADEON_USAGE_READWRITE);
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if (!cb[i])
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continue;
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/* COLOR_BASE */
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r600_write_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base);
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reloc = r600_context_bo_reloc(&rctx->b,
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&rctx->b.rings.gfx,
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(struct r600_resource*)cb[i]->base.texture,
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RADEON_USAGE_READWRITE);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc);
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/* FMASK */
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r600_write_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask);
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reloc = r600_context_bo_reloc(&rctx->b,
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&rctx->b.rings.gfx,
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cb[i]->cb_buffer_fmask,
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RADEON_USAGE_READWRITE);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc);
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/* CMASK */
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r600_write_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask);
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reloc = r600_context_bo_reloc(&rctx->b,
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&rctx->b.rings.gfx,
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cb[i]->cb_buffer_cmask,
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RADEON_USAGE_READWRITE);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc);
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}
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r600_write_context_reg_seq(cs, R_028060_CB_COLOR0_SIZE, nr_cbufs);
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for (i = 0; i < nr_cbufs; i++) {
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radeon_emit(cs, cb[i]->cb_color_size);
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radeon_emit(cs, cb[i] ? cb[i]->cb_color_size : 0);
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}
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r600_write_context_reg_seq(cs, R_028080_CB_COLOR0_VIEW, nr_cbufs);
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for (i = 0; i < nr_cbufs; i++) {
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radeon_emit(cs, cb[i]->cb_color_view);
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radeon_emit(cs, cb[i] ? cb[i]->cb_color_view : 0);
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}
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r600_write_context_reg_seq(cs, R_028100_CB_COLOR0_MASK, nr_cbufs);
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for (i = 0; i < nr_cbufs; i++) {
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radeon_emit(cs, cb[i]->cb_color_mask);
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}
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/* FMASK. */
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r600_write_context_reg_seq(cs, R_0280E0_CB_COLOR0_FRAG, nr_cbufs);
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for (i = 0; i < nr_cbufs; i++) {
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radeon_emit(cs, cb[i]->cb_color_fmask);
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}
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/* relocations */
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for (i = 0; i < nr_cbufs; i++) {
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unsigned reloc = r600_context_bo_reloc(&rctx->b,
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&rctx->b.rings.gfx,
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cb[i]->cb_buffer_fmask,
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RADEON_USAGE_READWRITE);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc);
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}
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/* CMASK. */
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r600_write_context_reg_seq(cs, R_0280C0_CB_COLOR0_TILE, nr_cbufs);
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for (i = 0; i < nr_cbufs; i++) {
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radeon_emit(cs, cb[i]->cb_color_cmask);
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}
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/* relocations */
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for (i = 0; i < nr_cbufs; i++) {
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unsigned reloc = r600_context_bo_reloc(&rctx->b,
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&rctx->b.rings.gfx,
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cb[i]->cb_buffer_cmask,
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RADEON_USAGE_READWRITE);
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radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
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radeon_emit(cs, reloc);
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radeon_emit(cs, cb[i] ? cb[i]->cb_color_mask : 0);
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}
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sbu |= SURFACE_BASE_UPDATE_COLOR_NUM(nr_cbufs);
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