fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-23 17:40:11 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: do not predicate FMASK decompression when DCC+MSAA is used

Browse source 
Even if the FCE predicate is FALSE, we might still need to decompress
FMASK if compressed rendering was used. FMASK decompressions should
never been predicated.

This fixes a ton of CTS failures and a rendering issue with Control
when DCC+MSAA is force-enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8331>
This commit is contained in:
Samuel Pitoiset 2021-01-05 14:28:53 +01:00 • committed by Marge Bot
parent 00064713a3
commit 6e7008e94b
1 changed files with 4 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/amd/vulkan/radv_meta_fast_clear.c
View file

@ -744,7 +744,8 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL); assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) { if ((decompress_dcc && radv_dcc_enabled(image, subresourceRange->baseMipLevel)) ||
(!(radv_image_has_fmask(image) && !image->tc_compatible_cmask))) {
uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset : uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
image->fce_pred_offset; image->fce_pred_offset;
pred_offset += 8 * subresourceRange->baseMipLevel; pred_offset += 8 * subresourceRange->baseMipLevel;
@ -758,7 +759,8 @@ radv_emit_color_decompress(struct radv_cmd_buffer *cmd_buffer,
radv_process_color_image(cmd_buffer, image, subresourceRange, radv_process_color_image(cmd_buffer, image, subresourceRange,
decompress_dcc); decompress_dcc);
if (radv_dcc_enabled(image, subresourceRange->baseMipLevel)) { if ((decompress_dcc && radv_dcc_enabled(image, subresourceRange->baseMipLevel)) ||
(!(radv_image_has_fmask(image) && !image->tc_compatible_cmask))) {
uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset : uint64_t pred_offset = decompress_dcc ? image->dcc_pred_offset :
image->fce_pred_offset; image->fce_pred_offset;
pred_offset += 8 * subresourceRange->baseMipLevel; pred_offset += 8 * subresourceRange->baseMipLevel;