From 6e29a2c8d54b301402fa37eb500633f7bf035cc9 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Mon, 3 Feb 2025 15:57:00 -0500 Subject: [PATCH] agx: switch to nir_tex_src_lod_bias_min_agx saves moves. Signed-off-by: Alyssa Rosenzweig Part-of: --- src/asahi/compiler/agx_compile.c | 28 +++++++++++++--------- src/asahi/compiler/agx_nir_lower_texture.c | 9 +++++++ 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index 4f3e9cd0b14..510579e8613 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -2173,8 +2173,7 @@ agx_emit_tex(agx_builder *b, nir_tex_instr *instr) agx_index coords = agx_null(), bindless = agx_immediate(0), texture = agx_immediate(instr->texture_index), sampler = agx_immediate(0), lod = agx_immediate(0), - compare = agx_null(), packed_offset = agx_null(), - min_lod = agx_null(); + compare = agx_null(), packed_offset = agx_null(); bool lod_is_zero = true; @@ -2197,9 +2196,9 @@ agx_emit_tex(agx_builder *b, nir_tex_instr *instr) nir_src_as_uint(instr->src[i].src) == 0; break; - case nir_tex_src_min_lod: - assert(index.size == AGX_SIZE_16); - min_lod = index; + case nir_tex_src_lod_bias_min_agx: + assert(index.size == AGX_SIZE_32); + lod = index; break; case nir_tex_src_comparator: @@ -2219,6 +2218,10 @@ agx_emit_tex(agx_builder *b, nir_tex_instr *instr) agx_translate_bindless_handle(b, &instr->src[i].src, &bindless); break; + case nir_tex_src_min_lod: + assert(instr->op == nir_texop_txd && "other cases lowered"); + break; + case nir_tex_src_ddx: { int y_idx = nir_tex_instr_src_index(instr, nir_tex_src_ddy); assert(y_idx >= 0 && "we only handle gradients"); @@ -2264,16 +2267,19 @@ agx_emit_tex(agx_builder *b, nir_tex_instr *instr) } } - enum agx_lod_mode lod_mode = agx_lod_mode_for_nir( - instr->op, nir_tex_instr_src_index(instr, nir_tex_src_bias) >= 0, - nir_tex_instr_src_index(instr, nir_tex_src_min_lod) >= 0, lod_is_zero); + bool has_min_lod = + nir_tex_instr_src_index(instr, nir_tex_src_lod_bias_min_agx) >= 0 || + nir_tex_instr_src_index(instr, nir_tex_src_min_lod) >= 0; + + bool has_bias = (has_min_lod && instr->op != nir_texop_txd) || + (nir_tex_instr_src_index(instr, nir_tex_src_bias) >= 0); + + enum agx_lod_mode lod_mode = + agx_lod_mode_for_nir(instr->op, has_bias, has_min_lod, lod_is_zero); if (lod_mode == AGX_LOD_MODE_AUTO_LOD) { /* Ignored logically but asserted 0 */ lod = agx_immediate(0); - } else if (lod_mode == AGX_LOD_MODE_AUTO_LOD_BIAS_MIN) { - /* Combine min with lod */ - lod = agx_vec2(b, lod, min_lod); } agx_index dst = agx_def_index(&instr->def); diff --git a/src/asahi/compiler/agx_nir_lower_texture.c b/src/asahi/compiler/agx_nir_lower_texture.c index 331a0ec8721..13852880555 100644 --- a/src/asahi/compiler/agx_nir_lower_texture.c +++ b/src/asahi/compiler/agx_nir_lower_texture.c @@ -321,6 +321,15 @@ lower_regular_texture(nir_builder *b, nir_instr *instr, UNUSED void *data) nir_tex_instr_add_src(tex, nir_tex_src_backend2, packed); } + if (nir_tex_instr_src_index(tex, nir_tex_src_bias) >= 0 && + nir_tex_instr_src_index(tex, nir_tex_src_min_lod) >= 0) { + + nir_def *bias = nir_steal_tex_src(tex, nir_tex_src_bias); + nir_def *min_lod = nir_steal_tex_src(tex, nir_tex_src_min_lod); + nir_def *packed = nir_pack_32_2x16_split(b, bias, min_lod); + nir_tex_instr_add_src(tex, nir_tex_src_lod_bias_min_agx, packed); + } + /* We reserve bound sampler #0, so we offset bound samplers by 1 and * otherwise map bound samplers as-is. */