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https://gitlab.freedesktop.org/mesa/mesa.git
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gallium: add opcode and types for 64-bit integers. (v3)
This just adds the basic support for 64-bit opcodes, and the new types. v2: add conversion opcodes. add documentation. v3: - make docs more consistent - change TGSI_OPCODE_I2U64 to TGSI_OPCODE_U2I64 Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2) Reviewed-by: Roland Scheidegger <sroland@vmware.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Dave Airlie
Nicolai Hähnle
parent
9694b23f66
commit
6e1a34d545
4 changed files with 362 additions and 20 deletions
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@ -59,8 +59,8 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
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{ 1, 3, 0, 0, 0, 0, 0, COMP, "FMA", TGSI_OPCODE_FMA },
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{ 1, 1, 0, 0, 0, 0, 0, REPL, "SQRT", TGSI_OPCODE_SQRT },
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{ 1, 3, 0, 0, 0, 0, 0, REPL, "DP2A", TGSI_OPCODE_DP2A },
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{ 0, 0, 0, 0, 0, 0, 0, NONE, "", 22 }, /* removed */
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{ 0, 0, 0, 0, 0, 0, 0, NONE, "", 23 }, /* removed */
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "F2U64", TGSI_OPCODE_F2U64 },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "F2I64", TGSI_OPCODE_F2I64 },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "FRC", TGSI_OPCODE_FRC },
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{ 1, 3, 0, 0, 0, 0, 0, COMP, "CLAMP", TGSI_OPCODE_CLAMP },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "FLR", TGSI_OPCODE_FLR },
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@ -69,9 +69,9 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
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{ 1, 1, 0, 0, 0, 0, 0, REPL, "LG2", TGSI_OPCODE_LG2 },
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{ 1, 2, 0, 0, 0, 0, 0, REPL, "POW", TGSI_OPCODE_POW },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "XPD", TGSI_OPCODE_XPD },
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{ 0, 0, 0, 0, 0, 0, 0, NONE, "", 32 }, /* removed */
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "U2I64", TGSI_OPCODE_U2I64 },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "ABS", TGSI_OPCODE_ABS },
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{ 0, 0, 0, 0, 0, 0, 0, NONE, "", 34 }, /* removed */
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "I2I64", TGSI_OPCODE_I2I64 },
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{ 1, 2, 0, 0, 0, 0, 0, REPL, "DPH", TGSI_OPCODE_DPH },
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{ 1, 1, 0, 0, 0, 0, 0, REPL, "COS", TGSI_OPCODE_COS },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "DDX", TGSI_OPCODE_DDX },
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@ -81,14 +81,14 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
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{ 1, 1, 0, 0, 0, 0, 0, REPL, "PK2US", TGSI_OPCODE_PK2US },
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{ 1, 1, 0, 0, 0, 0, 0, REPL, "PK4B", TGSI_OPCODE_PK4B },
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{ 1, 1, 0, 0, 0, 0, 0, REPL, "PK4UB", TGSI_OPCODE_PK4UB },
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{ 0, 1, 0, 0, 0, 0, 1, NONE, "", 44 }, /* removed */
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{ 1, 1, 0, 0, 0, 0, 1, COMP, "D2U64", TGSI_OPCODE_D2U64 },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "SEQ", TGSI_OPCODE_SEQ },
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{ 0, 1, 0, 0, 0, 0, 1, NONE, "", 46 }, /* removed */
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{ 1, 1, 0, 0, 0, 0, 1, COMP, "D2I64", TGSI_OPCODE_D2I64 },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "SGT", TGSI_OPCODE_SGT },
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{ 1, 1, 0, 0, 0, 0, 0, REPL, "SIN", TGSI_OPCODE_SIN },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "SLE", TGSI_OPCODE_SLE },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "SNE", TGSI_OPCODE_SNE },
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{ 0, 1, 0, 0, 0, 0, 1, NONE, "", 51 }, /* removed */
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{ 1, 1, 0, 0, 0, 0, 1, COMP, "U642D", TGSI_OPCODE_U642D },
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{ 1, 2, 1, 0, 0, 0, 0, OTHR, "TEX", TGSI_OPCODE_TEX },
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{ 1, 4, 1, 0, 0, 0, 0, OTHR, "TXD", TGSI_OPCODE_TXD },
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{ 1, 2, 1, 0, 0, 0, 0, OTHR, "TXP", TGSI_OPCODE_TXP },
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@ -96,10 +96,10 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
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{ 1, 1, 0, 0, 0, 0, 0, CHAN, "UP2US", TGSI_OPCODE_UP2US },
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{ 1, 1, 0, 0, 0, 0, 0, CHAN, "UP4B", TGSI_OPCODE_UP4B },
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{ 1, 1, 0, 0, 0, 0, 0, CHAN, "UP4UB", TGSI_OPCODE_UP4UB },
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{ 0, 1, 0, 0, 0, 0, 1, NONE, "", 59 }, /* removed */
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{ 0, 1, 0, 0, 0, 0, 1, NONE, "", 60 }, /* removed */
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{ 1, 1, 0, 0, 0, 0, 1, COMP, "U642F", TGSI_OPCODE_U642F },
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{ 1, 1, 0, 0, 0, 0, 1, COMP, "I642F", TGSI_OPCODE_I642F },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "ARR", TGSI_OPCODE_ARR },
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{ 0, 1, 0, 0, 0, 0, 1, NONE, "", 62 }, /* removed */
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{ 1, 1, 0, 0, 0, 0, 1, COMP, "I642D", TGSI_OPCODE_I642D },
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{ 0, 0, 0, 0, 1, 0, 0, NONE, "CAL", TGSI_OPCODE_CAL },
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{ 0, 0, 0, 0, 0, 0, 0, NONE, "RET", TGSI_OPCODE_RET },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "SSG", TGSI_OPCODE_SSG },
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@ -265,6 +265,28 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "VOTE_ANY", TGSI_OPCODE_VOTE_ANY },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "VOTE_ALL", TGSI_OPCODE_VOTE_ALL },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "VOTE_EQ", TGSI_OPCODE_VOTE_EQ },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64SEQ", TGSI_OPCODE_U64SEQ },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64SNE", TGSI_OPCODE_U64SNE },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "I64SLT", TGSI_OPCODE_I64SLT },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64SLT", TGSI_OPCODE_U64SLT },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "I64SGE", TGSI_OPCODE_I64SGE },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64SGE", TGSI_OPCODE_U64SGE },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "I64MIN", TGSI_OPCODE_I64MIN },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64MIN", TGSI_OPCODE_U64MIN },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "I64MAX", TGSI_OPCODE_I64MAX },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64MAX", TGSI_OPCODE_U64MAX },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "I64ABS", TGSI_OPCODE_I64ABS },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "I64SSG", TGSI_OPCODE_I64SSG },
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{ 1, 1, 0, 0, 0, 0, 0, COMP, "I64NEG", TGSI_OPCODE_I64NEG },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64ADD", TGSI_OPCODE_U64ADD },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64MUL", TGSI_OPCODE_U64MUL },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64SHL", TGSI_OPCODE_U64SHL },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "I64SHR", TGSI_OPCODE_I64SHR },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64SHR", TGSI_OPCODE_U64SHR },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "I64DIV", TGSI_OPCODE_I64DIV },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64DIV", TGSI_OPCODE_U64DIV },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "I64MOD", TGSI_OPCODE_I64MOD },
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{ 1, 2, 0, 0, 0, 0, 0, COMP, "U64MOD", TGSI_OPCODE_U64MOD },
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};
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const struct tgsi_opcode_info *
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@ -382,6 +404,12 @@ tgsi_opcode_infer_type( uint opcode )
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case TGSI_OPCODE_DSGE:
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case TGSI_OPCODE_DSLT:
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case TGSI_OPCODE_DSNE:
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case TGSI_OPCODE_U64SEQ:
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case TGSI_OPCODE_U64SNE:
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case TGSI_OPCODE_U64SLT:
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case TGSI_OPCODE_U64SGE:
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case TGSI_OPCODE_I64SLT:
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case TGSI_OPCODE_I64SGE:
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return TGSI_TYPE_SIGNED;
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case TGSI_OPCODE_DADD:
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case TGSI_OPCODE_DABS:
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@ -405,7 +433,33 @@ tgsi_opcode_infer_type( uint opcode )
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case TGSI_OPCODE_F2D:
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case TGSI_OPCODE_I2D:
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case TGSI_OPCODE_U2D:
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case TGSI_OPCODE_U642D:
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case TGSI_OPCODE_I642D:
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return TGSI_TYPE_DOUBLE;
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case TGSI_OPCODE_U64MAX:
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case TGSI_OPCODE_U64MIN:
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case TGSI_OPCODE_U64ADD:
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case TGSI_OPCODE_U64MUL:
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case TGSI_OPCODE_U64DIV:
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case TGSI_OPCODE_U64MOD:
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case TGSI_OPCODE_U64SHL:
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case TGSI_OPCODE_U64SHR:
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case TGSI_OPCODE_F2U64:
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case TGSI_OPCODE_D2U64:
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return TGSI_TYPE_UNSIGNED64;
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case TGSI_OPCODE_I64MAX:
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case TGSI_OPCODE_I64MIN:
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case TGSI_OPCODE_I64ABS:
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case TGSI_OPCODE_I64SSG:
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case TGSI_OPCODE_I64NEG:
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case TGSI_OPCODE_I64SHR:
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case TGSI_OPCODE_I64DIV:
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case TGSI_OPCODE_I64MOD:
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case TGSI_OPCODE_F2I64:
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case TGSI_OPCODE_U2I64:
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case TGSI_OPCODE_I2I64:
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case TGSI_OPCODE_D2I64:
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return TGSI_TYPE_SIGNED64;
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default:
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return TGSI_TYPE_FLOAT;
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}
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@ -430,10 +484,12 @@ tgsi_opcode_infer_src_type( uint opcode )
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case TGSI_OPCODE_SAMPLE_I_MS:
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case TGSI_OPCODE_UMUL_HI:
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case TGSI_OPCODE_UP2H:
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case TGSI_OPCODE_U2I64:
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return TGSI_TYPE_UNSIGNED;
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case TGSI_OPCODE_IMUL_HI:
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case TGSI_OPCODE_I2F:
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case TGSI_OPCODE_I2D:
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case TGSI_OPCODE_I2I64:
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return TGSI_TYPE_SIGNED;
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case TGSI_OPCODE_ARL:
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case TGSI_OPCODE_ARR:
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@ -446,6 +502,8 @@ tgsi_opcode_infer_src_type( uint opcode )
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case TGSI_OPCODE_FSLT:
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case TGSI_OPCODE_FSNE:
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case TGSI_OPCODE_UCMP:
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case TGSI_OPCODE_F2U64:
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case TGSI_OPCODE_F2I64:
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return TGSI_TYPE_FLOAT;
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case TGSI_OPCODE_D2F:
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case TGSI_OPCODE_D2U:
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@ -454,7 +512,21 @@ tgsi_opcode_infer_src_type( uint opcode )
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case TGSI_OPCODE_DSGE:
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case TGSI_OPCODE_DSLT:
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case TGSI_OPCODE_DSNE:
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case TGSI_OPCODE_D2U64:
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case TGSI_OPCODE_D2I64:
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return TGSI_TYPE_DOUBLE;
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case TGSI_OPCODE_U64SEQ:
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case TGSI_OPCODE_U64SNE:
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case TGSI_OPCODE_U64SLT:
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case TGSI_OPCODE_U64SGE:
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case TGSI_OPCODE_U642F:
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case TGSI_OPCODE_U642D:
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return TGSI_TYPE_UNSIGNED64;
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case TGSI_OPCODE_I64SLT:
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case TGSI_OPCODE_I64SGE:
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case TGSI_OPCODE_I642F:
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case TGSI_OPCODE_I642D:
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return TGSI_TYPE_SIGNED64;
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default:
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return tgsi_opcode_infer_type(opcode);
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}
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@ -98,7 +98,9 @@ enum tgsi_opcode_type {
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TGSI_TYPE_UNSIGNED,
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TGSI_TYPE_SIGNED,
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TGSI_TYPE_FLOAT,
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TGSI_TYPE_DOUBLE
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TGSI_TYPE_DOUBLE,
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TGSI_TYPE_UNSIGNED64,
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TGSI_TYPE_SIGNED64,
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};
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static inline bool tgsi_type_is_64bit(enum tgsi_opcode_type type)
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@ -2082,6 +2082,246 @@ Perform a * b + c with no intermediate rounding step.
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dst.y = unsigned(src0.zw)
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64-bit Integer ISA
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^^^^^^^^^^^^^^^^^^
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The 64-bit integer opcodes reinterpret four-component vectors into
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two-component vectors with 64-bits in each component.
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.. opcode:: I64ABS - 64-bit Integer Absolute Value
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dst.xy = |src0.xy|
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dst.zw = |src0.zw|
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.. opcode:: I64NEG - 64-bit Integer Negate
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Two's complement.
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.. math::
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dst.xy = -src.xy
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dst.zw = -src.zw
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.. opcode:: I64SSG - 64-bit Integer Set Sign
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.. math::
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dst.xy = (src0.xy < 0) ? -1 : (src0.xy > 0) ? 1 : 0
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dst.zw = (src0.zw < 0) ? -1 : (src0.zw > 0) ? 1 : 0
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.. opcode:: U64ADD - 64-bit Integer Add
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.. math::
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dst.xy = src0.xy + src1.xy
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dst.zw = src0.zw + src1.zw
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.. opcode:: U64MUL - 64-bit Integer Multiply
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.. math::
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dst.xy = src0.xy * src1.xy
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dst.zw = src0.zw * src1.zw
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.. opcode:: U64SEQ - 64-bit Integer Set on Equal
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.. math::
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dst.x = src0.xy == src1.xy ? \sim 0 : 0
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dst.z = src0.zw == src1.zw ? \sim 0 : 0
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.. opcode:: U64SNE - 64-bit Integer Set on Not Equal
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.. math::
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dst.x = src0.xy != src1.xy ? \sim 0 : 0
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dst.z = src0.zw != src1.zw ? \sim 0 : 0
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.. opcode:: U64SLT - 64-bit Unsigned Integer Set on Less Than
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.. math::
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dst.x = src0.xy < src1.xy ? \sim 0 : 0
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dst.z = src0.zw < src1.zw ? \sim 0 : 0
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.. opcode:: U64SGE - 64-bit Unsigned Integer Set on Greater Equal
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.. math::
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dst.x = src0.xy >= src1.xy ? \sim 0 : 0
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dst.z = src0.zw >= src1.zw ? \sim 0 : 0
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.. opcode:: I64SLT - 64-bit Signed Integer Set on Less Than
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.. math::
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dst.x = src0.xy < src1.xy ? \sim 0 : 0
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dst.z = src0.zw < src1.zw ? \sim 0 : 0
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.. opcode:: I64SGE - 64-bit Signed Integer Set on Greater Equal
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.. math::
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dst.x = src0.xy >= src1.xy ? \sim 0 : 0
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dst.z = src0.zw >= src1.zw ? \sim 0 : 0
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.. opcode:: I64MIN - Minimum of 64-bit Signed Integers
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.. math::
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dst.xy = min(src0.xy, src1.xy)
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dst.zw = min(src0.zw, src1.zw)
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.. opcode:: U64MIN - Minimum of 64-bit Unsigned Integers
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.. math::
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dst.xy = min(src0.xy, src1.xy)
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dst.zw = min(src0.zw, src1.zw)
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.. opcode:: I64MAX - Maximum of 64-bit Signed Integers
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.. math::
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dst.xy = max(src0.xy, src1.xy)
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dst.zw = max(src0.zw, src1.zw)
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.. opcode:: U64MAX - Maximum of 64-bit Unsigned Integers
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.. math::
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dst.xy = max(src0.xy, src1.xy)
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dst.zw = max(src0.zw, src1.zw)
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.. opcode:: U64SHL - Shift Left 64-bit Unsigned Integer
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The shift count is masked with 0x3f before the shift is applied.
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.. math::
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dst.xy = src0.xy << (0x3f \& src1.x)
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dst.zw = src0.zw << (0x3f \& src1.y)
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.. opcode:: I64SHR - Arithmetic Shift Right (of 64-bit Signed Integer)
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The shift count is masked with 0x3f before the shift is applied.
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.. math::
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dst.xy = src0.xy >> (0x3f \& src1.x)
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dst.zw = src0.zw >> (0x3f \& src1.y)
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.. opcode:: U64SHR - Logical Shift Right (of 64-bit Unsigned Integer)
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The shift count is masked with 0x3f before the shift is applied.
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.. math::
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dst.xy = src0.xy >> (unsigned) (0x3f \& src1.x)
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dst.zw = src0.zw >> (unsigned) (0x3f \& src1.y)
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.. opcode:: I64DIV - 64-bit Signed Integer Division
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.. math::
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dst.xy = src0.xy \ src1.xy
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dst.zw = src0.zw \ src1.zw
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.. opcode:: U64DIV - 64-bit Unsigned Integer Division
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.. math::
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dst.xy = src0.xy \ src1.xy
|
||||
dst.zw = src0.zw \ src1.zw
|
||||
|
||||
.. opcode:: U64MOD - 64-bit Unsigned Integer Remainder
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = src0.xy \bmod src1.xy
|
||||
dst.zw = src0.zw \bmod src1.zw
|
||||
|
||||
.. opcode:: I64MOD - 64-bit Signed Integer Remainder
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = src0.xy \bmod src1.xy
|
||||
dst.zw = src0.zw \bmod src1.zw
|
||||
|
||||
.. opcode:: F2U64 - Float to 64-bit Unsigned Int
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = (uint64_t) src0.x
|
||||
dst.zw = (uint64_t) src0.y
|
||||
|
||||
.. opcode:: F2I64 - Float to 64-bit Int
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = (int64_t) src0.x
|
||||
dst.zw = (int64_t) src0.y
|
||||
|
||||
.. opcode:: U2I64 - Unsigned Integer to 64-bit Integer
|
||||
|
||||
This is a zero extension.
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = (uint64_t) src0.x
|
||||
dst.zw = (uint64_t) src0.y
|
||||
|
||||
.. opcode:: I2I64 - Signed Integer to 64-bit Integer
|
||||
|
||||
This is a sign extension.
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = (int64_t) src0.x
|
||||
dst.zw = (int64_t) src0.y
|
||||
|
||||
.. opcode:: D2U64 - Double to 64-bit Unsigned Int
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = (uint64_t) src0.xy
|
||||
dst.zw = (uint64_t) src0.zw
|
||||
|
||||
.. opcode:: D2I64 - Double to 64-bit Int
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = (int64_t) src0.xy
|
||||
dst.zw = (int64_t) src0.zw
|
||||
|
||||
.. opcode:: U642F - 64-bit unsigned integer to float
|
||||
|
||||
.. math::
|
||||
|
||||
dst.x = (float) src0.xy
|
||||
dst.y = (float) src0.zw
|
||||
|
||||
.. opcode:: I642F - 64-bit Int to Float
|
||||
|
||||
.. math::
|
||||
|
||||
dst.x = (float) src0.xy
|
||||
dst.y = (float) src0.zw
|
||||
|
||||
.. opcode:: U642D - 64-bit unsigned integer to double
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = (double) src0.xy
|
||||
dst.zw = (double) src0.zw
|
||||
|
||||
.. opcode:: I642D - 64-bit Int to double
|
||||
|
||||
.. math::
|
||||
|
||||
dst.xy = (double) src0.xy
|
||||
dst.zw = (double) src0.zw
|
||||
|
||||
.. _samplingopcodes:
|
||||
|
||||
Resource Sampling Opcodes
|
||||
|
|
|
|||
|
|
@ -345,7 +345,8 @@ struct tgsi_property_data {
|
|||
#define TGSI_OPCODE_FMA 19
|
||||
#define TGSI_OPCODE_SQRT 20
|
||||
#define TGSI_OPCODE_DP2A 21
|
||||
/* gap */
|
||||
#define TGSI_OPCODE_F2U64 22
|
||||
#define TGSI_OPCODE_F2I64 23
|
||||
#define TGSI_OPCODE_FRC 24
|
||||
#define TGSI_OPCODE_CLAMP 25
|
||||
#define TGSI_OPCODE_FLR 26
|
||||
|
|
@ -354,9 +355,9 @@ struct tgsi_property_data {
|
|||
#define TGSI_OPCODE_LG2 29
|
||||
#define TGSI_OPCODE_POW 30
|
||||
#define TGSI_OPCODE_XPD 31
|
||||
/* gap */
|
||||
#define TGSI_OPCODE_U2I64 32
|
||||
#define TGSI_OPCODE_ABS 33
|
||||
/* gap */
|
||||
#define TGSI_OPCODE_I2I64 34
|
||||
#define TGSI_OPCODE_DPH 35
|
||||
#define TGSI_OPCODE_COS 36
|
||||
#define TGSI_OPCODE_DDX 37
|
||||
|
|
@ -366,14 +367,14 @@ struct tgsi_property_data {
|
|||
#define TGSI_OPCODE_PK2US 41
|
||||
#define TGSI_OPCODE_PK4B 42
|
||||
#define TGSI_OPCODE_PK4UB 43
|
||||
/* gap */
|
||||
#define TGSI_OPCODE_D2U64 44
|
||||
#define TGSI_OPCODE_SEQ 45
|
||||
/* gap */
|
||||
#define TGSI_OPCODE_D2I64 46
|
||||
#define TGSI_OPCODE_SGT 47
|
||||
#define TGSI_OPCODE_SIN 48
|
||||
#define TGSI_OPCODE_SLE 49
|
||||
#define TGSI_OPCODE_SNE 50
|
||||
/* gap */
|
||||
#define TGSI_OPCODE_U642D 51
|
||||
#define TGSI_OPCODE_TEX 52
|
||||
#define TGSI_OPCODE_TXD 53
|
||||
#define TGSI_OPCODE_TXP 54
|
||||
|
|
@ -381,9 +382,10 @@ struct tgsi_property_data {
|
|||
#define TGSI_OPCODE_UP2US 56
|
||||
#define TGSI_OPCODE_UP4B 57
|
||||
#define TGSI_OPCODE_UP4UB 58
|
||||
/* gap */
|
||||
#define TGSI_OPCODE_U642F 59
|
||||
#define TGSI_OPCODE_I642F 60
|
||||
#define TGSI_OPCODE_ARR 61
|
||||
/* gap */
|
||||
#define TGSI_OPCODE_I642D 62
|
||||
#define TGSI_OPCODE_CAL 63
|
||||
#define TGSI_OPCODE_RET 64
|
||||
#define TGSI_OPCODE_SSG 65 /* SGN */
|
||||
|
|
@ -568,7 +570,33 @@ struct tgsi_property_data {
|
|||
#define TGSI_OPCODE_VOTE_ALL 224
|
||||
#define TGSI_OPCODE_VOTE_EQ 225
|
||||
|
||||
#define TGSI_OPCODE_LAST 226
|
||||
#define TGSI_OPCODE_U64SEQ 226
|
||||
#define TGSI_OPCODE_U64SNE 227
|
||||
#define TGSI_OPCODE_I64SLT 228
|
||||
#define TGSI_OPCODE_U64SLT 229
|
||||
#define TGSI_OPCODE_I64SGE 230
|
||||
#define TGSI_OPCODE_U64SGE 231
|
||||
|
||||
#define TGSI_OPCODE_I64MIN 232
|
||||
#define TGSI_OPCODE_U64MIN 233
|
||||
#define TGSI_OPCODE_I64MAX 234
|
||||
#define TGSI_OPCODE_U64MAX 235
|
||||
|
||||
#define TGSI_OPCODE_I64ABS 236
|
||||
#define TGSI_OPCODE_I64SSG 237
|
||||
#define TGSI_OPCODE_I64NEG 238
|
||||
|
||||
#define TGSI_OPCODE_U64ADD 239
|
||||
#define TGSI_OPCODE_U64MUL 240
|
||||
#define TGSI_OPCODE_U64SHL 241
|
||||
#define TGSI_OPCODE_I64SHR 242
|
||||
#define TGSI_OPCODE_U64SHR 243
|
||||
|
||||
#define TGSI_OPCODE_I64DIV 244
|
||||
#define TGSI_OPCODE_U64DIV 245
|
||||
#define TGSI_OPCODE_I64MOD 246
|
||||
#define TGSI_OPCODE_U64MOD 247
|
||||
#define TGSI_OPCODE_LAST 248
|
||||
|
||||
/**
|
||||
* Opcode is the operation code to execute. A given operation defines the
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue