From 6da19eafd50d9dcf4abcaf6cba7cc3dbcd307adc Mon Sep 17 00:00:00 2001 From: Gert Wollny Date: Sun, 22 Dec 2024 23:41:37 +0100 Subject: [PATCH] r600/sfn: gather info and set lowering 64 bit after nir_lower_io After nir_lower_io we need to gather the info about 64 bit usage to be up-to-date when deciding whether the remaining 64 bit IO ops be lowered. Before 89dad5618ddb ("gallium: add PIPE_CAP_CALL_FINALIZE_NIR_IN_LINKER") the info was eventually updated to include the use of 64 bit values also if only some IO was using this so that SFN was handling the code correctly. As it seems with above patch this is not always the case anymore, and we have to take care of it. Fixes: 89dad5618ddb ("gallium: add PIPE_CAP_CALL_FINALIZE_NIR_IN_LINKER") Signed-off-by: Gert Wollny Part-of: --- src/gallium/drivers/r600/sfn/sfn_nir.cpp | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp index 85ca58ac78a..20000454e1b 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp @@ -742,10 +742,6 @@ r600_lower_and_optimize_nir(nir_shader *sh, enum amd_gfx_level gfx_level, struct pipe_stream_output_info *so_info) { - bool lower_64bit = - gfx_level < CAYMAN && - (sh->options->lower_int64_options || sh->options->lower_doubles_options) && - ((sh->info.bit_sizes_float | sh->info.bit_sizes_int) & 64); r600::sort_uniforms(sh); NIR_PASS_V(sh, r600_nir_fix_kcache_indirect_access); @@ -775,6 +771,13 @@ r600_lower_and_optimize_nir(nir_shader *sh, (nir_lower_io_lower_64bit_to_32 | nir_lower_io_use_interpolated_input_intrinsics)); + nir_shader_gather_info(sh, nir_shader_get_entrypoint(sh)); + + bool lower_64bit_io_to_vec2 = (sh->info.bit_sizes_float | sh->info.bit_sizes_int) & 64; + bool lower_64bit = + gfx_level < CAYMAN && + (sh->options->lower_int64_options || sh->options->lower_doubles_options) && + lower_64bit_io_to_vec2; if (sh->info.stage == MESA_SHADER_FRAGMENT) NIR_PASS_V(sh, r600_lower_fs_pos_input); @@ -823,7 +826,7 @@ r600_lower_and_optimize_nir(nir_shader *sh, NIR_PASS_V(sh, r600_nir_lower_int_tg4); NIR_PASS_V(sh, r600::r600_nir_lower_tex_to_backend, gfx_level); - if ((sh->info.bit_sizes_float | sh->info.bit_sizes_int) & 64) { + if (lower_64bit_io_to_vec2) { NIR_PASS_V(sh, r600::r600_nir_split_64bit_io); NIR_PASS_V(sh, r600::r600_split_64bit_alu_and_phi); NIR_PASS_V(sh, nir_split_64bit_vec3_and_vec4); @@ -836,7 +839,7 @@ r600_lower_and_optimize_nir(nir_shader *sh, if (lower_64bit) NIR_PASS_V(sh, r600::r600_nir_64_to_vec2); - if ((sh->info.bit_sizes_float | sh->info.bit_sizes_int) & 64) + if (lower_64bit_io_to_vec2) NIR_PASS_V(sh, r600::r600_split_64bit_uniforms_and_ubo); /* Lower to scalar to let some optimization work out better */