diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_compute.cc b/src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
index 5a46939abc1..d3998517c0d 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
@@ -312,6 +312,31 @@ fd6_compute_state_delete(struct pipe_context *pctx, void *_hwcso)
    free(hwcso);
 }
 
+static void
+fd6_get_compute_state_info(struct pipe_context *pctx, void *cso, struct pipe_compute_state_object_info *info)
+{
+   static struct ir3_shader_key key; /* static is implicitly zeroed */
+   struct fd6_compute_state *cs = (struct fd6_compute_state *)cso;
+   struct ir3_shader_state *hwcso = (struct ir3_shader_state *)cs->hwcso;
+   struct ir3_shader_variant *v = ir3_shader_variant(ir3_get_shader(hwcso), key, false, &pctx->debug);
+   struct fd_context *ctx = fd_context(pctx);
+   uint32_t threadsize_base = ctx->screen->info->threadsize_base;
+
+   info->max_threads = threadsize_base * ctx->screen->info->max_waves;
+   info->simd_sizes = threadsize_base;
+   info->preferred_simd_size = threadsize_base;
+
+   if (ctx->screen->info->a6xx.supports_double_threadsize &&
+       v->info.double_threadsize) {
+
+      info->max_threads *= 2;
+      info->simd_sizes |= (threadsize_base * 2);
+      info->preferred_simd_size *= 2;
+   }
+
+   info->private_memory = v->pvtmem_size;
+}
+
 template <chip CHIP>
 void
 fd6_compute_init(struct pipe_context *pctx)
@@ -322,5 +347,6 @@ fd6_compute_init(struct pipe_context *pctx)
    ctx->launch_grid = fd6_launch_grid<CHIP>;
    pctx->create_compute_state = fd6_compute_state_create;
    pctx->delete_compute_state = fd6_compute_state_delete;
+   pctx->get_compute_state_info = fd6_get_compute_state_info;
 }
 FD_GENX(fd6_compute_init);