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radv/amdgpu: bypass GL2 for command buffer BOs

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Better for latency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39674>
This commit is contained in:
Samuel Pitoiset 2026-02-03 12:05:33 +01:00 • committed by Marge Bot
parent f242a204ea
commit 6d7a1bc6ef
1 changed files with 3 additions and 2 deletions
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5
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
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@ -239,8 +239,9 @@ radv_amdgpu_cs_bo_create(struct radv_amdgpu_cs *cs, uint32_t ib_size)
const bool avoid_vram = cs->is_secondary && !can_always_use_ib2;
const enum radeon_bo_domain domain = avoid_vram ? RADEON_DOMAIN_GTT : radv_amdgpu_cs_domain(ws);
const enum radeon_bo_flag gtt_wc_flag = avoid_vram ? 0 : RADEON_FLAG_GTT_WC;
const enum radeon_bo_flag flags =
RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | gtt_wc_flag;
/* Bypass GL2 because command buffers are read only once and it's better for latency. */
const enum radeon_bo_flag flags = RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING |
RADEON_FLAG_READ_ONLY | RADEON_FLAG_GL2_BYPASS | gtt_wc_flag;
return ws->buffer_create(ws, ib_size, cs->ws->info.ip[cs->hw_ip].ib_alignment, domain, flags, RADV_BO_PRIORITY_CS, 0,
&cs->ib_buffer);