fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-08 12:00:35 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

zink: use dynamic state for line-width

Browse source 
This will lead to fewer pipelines in the cache, which is assumed to
become our most unavoidable performance bottle-neck down the line.

Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Erik Faye-Lund 2019-10-29 12:43:56 +01:00
parent d2bb63c8d4
commit 6d30abb4f1
5 changed files with 17 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
src/gallium/drivers/zink/zink_context.c
View file

@ -1020,8 +1020,10 @@ zink_draw_vbo(struct pipe_context *pctx,
&ctx->gfx_pipeline_state,
dinfo->mode);
enum pipe_prim_type reduced_prim = u_reduced_prim(dinfo->mode);
bool depth_bias = false;
switch (u_reduced_prim(dinfo->mode)) {
switch (reduced_prim) {
case PIPE_PRIM_POINTS:
depth_bias = rast_state->offset_point;
break;
@ -1154,6 +1156,13 @@ zink_draw_vbo(struct pipe_context *pctx,
vkCmdSetScissor(batch->cmdbuf, 0, 1, &fb_scissor);
}
if (reduced_prim == PIPE_PRIM_LINES) {
if (screen->feats.wideLines || ctx->line_width == 1.0f)
vkCmdSetLineWidth(batch->cmdbuf, ctx->line_width);
else
debug_printf("BUG: wide lines not supported, needs fallback!");
}
vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_FRONT_BIT, ctx->stencil_ref.ref_value[0]);
vkCmdSetStencilReference(batch->cmdbuf, VK_STENCIL_FACE_BACK_BIT, ctx->stencil_ref.ref_value[1]);

1
src/gallium/drivers/zink/zink_context.h
View file

@ -103,6 +103,7 @@ struct zink_context {
struct pipe_sampler_view *image_views[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_SAMPLER_VIEWS];
unsigned num_image_views[PIPE_SHADER_TYPES];
float line_width;
float blend_constants[4];
struct pipe_stencil_ref stencil_ref;

14
src/gallium/drivers/zink/zink_pipeline.c
View file

@ -85,12 +85,7 @@ zink_create_gfx_pipeline(struct zink_screen *screen,
rast_state.depthBiasConstantFactor = 0.0;
rast_state.depthBiasClamp = 0.0;
rast_state.depthBiasSlopeFactor = 0.0;
if (screen->feats.wideLines)
rast_state.lineWidth = state->line_width;
else {
debug_printf("BUG: wide lines not supported, needs fallback!");
rast_state.lineWidth = 1.0f;
}
rast_state.lineWidth = 1.0f;
VkPipelineDepthStencilStateCreateInfo depth_stencil_state = {};
depth_stencil_state.sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO;
@ -105,11 +100,12 @@ zink_create_gfx_pipeline(struct zink_screen *screen,
depth_stencil_state.depthWriteEnable = state->depth_stencil_alpha_state->depth_write;
VkDynamicState dynamicStateEnables[] = {
VK_DYNAMIC_STATE_DEPTH_BIAS,
VK_DYNAMIC_STATE_SCISSOR,
VK_DYNAMIC_STATE_STENCIL_REFERENCE,
VK_DYNAMIC_STATE_VIEWPORT,
VK_DYNAMIC_STATE_SCISSOR,
VK_DYNAMIC_STATE_LINE_WIDTH,
VK_DYNAMIC_STATE_DEPTH_BIAS,
VK_DYNAMIC_STATE_BLEND_CONSTANTS,
VK_DYNAMIC_STATE_STENCIL_REFERENCE,
};
VkPipelineDynamicStateCreateInfo pipelineDynamicStateCreateInfo = {};

2
src/gallium/drivers/zink/zink_pipeline.h
View file

@ -49,8 +49,6 @@ struct zink_gfx_pipeline_state {
struct zink_depth_stencil_alpha_state *depth_stencil_alpha_state;
float line_width;
VkSampleMask sample_mask;
uint8_t rast_samples;
};

2
src/gallium/drivers/zink/zink_state.c
View file

@ -424,7 +424,7 @@ zink_bind_rasterizer_state(struct pipe_context *pctx, void *cso)
if (ctx->rast_state) {
ctx->gfx_pipeline_state.rast_state = &ctx->rast_state->hw_state;
ctx->gfx_pipeline_state.line_width = ctx->rast_state->line_width;
ctx->line_width = ctx->rast_state->line_width;
}
}