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tu,freedreno: Don't fallback to LINEAR with DRM_FORMAT_MOD_QCOM_COMPRESSED

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DRM_FORMAT_MOD_QCOM_COMPRESSED forces the image to be UBWC regardless
of what's better for perf, we should respect that.

The regression is seen in GTK4 when it tries to create tiny swapchain
images.

Fixes: fc50fb35b0
("tu,freedreno: Enable linear mipmap tail for UBWC images")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34628>
(cherry picked from commit 36f22cc951)
This commit is contained in:
Danylo Piliaiev 2025-04-21 11:23:51 +02:00 • committed by Eric Engestrom
parent 559d33b2b6
commit 6cf01adf6b
7 changed files with 13 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -354,7 +354,7 @@
"description": "tu,freedreno: Don't fallback to LINEAR with DRM_FORMAT_MOD_QCOM_COMPRESSED",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "fc50fb35b0526a10da5e5fe72d4291c5175a9759",
"notes": null

5
src/freedreno/fdl/fd6_layout.c
View file

@ -118,6 +118,7 @@ fdl6_layout(struct fdl_layout *layout, const struct fd_dev_info *info,
enum pipe_format format, uint32_t nr_samples, uint32_t width0,
uint32_t height0, uint32_t depth0, uint32_t mip_levels,
uint32_t array_size, bool is_3d, bool is_mutable,
bool force_ubwc,
struct fdl_explicit_layout *explicit_layout)
{
uint32_t offset = 0, heightalign;
@ -149,7 +150,9 @@ fdl6_layout(struct fdl_layout *layout, const struct fd_dev_info *info,
if (ubwc_blockwidth == 0)
layout->ubwc = false;
if (width0 < FDL_MIN_UBWC_WIDTH) {
assert(!force_ubwc || layout->ubwc);
if (!force_ubwc && width0 < FDL_MIN_UBWC_WIDTH) {
layout->ubwc = false;
/* Linear D/S is not supported by HW. */
if (!util_format_is_depth_or_stencil(format))

2
src/freedreno/fdl/fd_layout_test.c
View file

@ -34,7 +34,7 @@ fdl_test_layout(const struct testcase *testcase, const struct fd_dev_id *dev_id)
MAX2(testcase->layout.nr_samples, 1), testcase->layout.width0,
MAX2(testcase->layout.height0, 1),
MAX2(testcase->layout.depth0, 1), mip_levels,
MAX2(testcase->array_size, 1), testcase->is_3d, false, NULL);
MAX2(testcase->array_size, 1), testcase->is_3d, false, false, NULL);
} else {
assert(fd_dev_gen(dev_id) >= 5);
fdl5_layout(&layout, testcase->format,

1
src/freedreno/fdl/freedreno_layout.h
View file

@ -241,6 +241,7 @@ bool fdl6_layout(struct fdl_layout *layout, const struct fd_dev_info *info,
enum pipe_format format, uint32_t nr_samples, uint32_t width0,
uint32_t height0, uint32_t depth0, uint32_t mip_levels,
uint32_t array_size, bool is_3d, bool is_mutable,
bool force_ubwc,
struct fdl_explicit_layout *plane_layout);
static inline void

1
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -2961,6 +2961,7 @@ tu_copy_image_to_image(struct tu_cmd_buffer *cmd,
layer_count,
extent.depth > 1,
false,
false,
NULL);
struct tu_bo *staging_bo;

3
src/freedreno/vulkan/tu_image.cc
View file

@ -500,9 +500,11 @@ tu_image_update_layout(struct tu_device *device, struct tu_image *image,
* but gralloc doesn't know this. So if we are explicitly told that it is
* UBWC, then override how the image was created.
*/
bool force_ubwc = false;
if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) {
assert(!image->force_linear_tile);
image->ubwc_enabled = true;
force_ubwc = true;
}
/* R8G8 images have a special tiled layout which we don't implement yet in
@ -548,6 +550,7 @@ tu_image_update_layout(struct tu_device *device, struct tu_image *image,
image->vk.array_layers,
image->vk.image_type == VK_IMAGE_TYPE_3D,
image->is_mutable,
force_ubwc,
plane_layouts ? &plane_layout : NULL)) {
assert(plane_layouts); /* can only fail with explicit layout */
return vk_error(device, VK_ERROR_INVALID_DRM_FORMAT_MODIFIER_PLANE_LAYOUT_EXT);

4
src/gallium/drivers/freedreno/a6xx/fd6_resource.cc
View file

@ -256,7 +256,7 @@ fd6_setup_slices(struct fd_resource *rsc)
fdl6_layout(&rsc->layout, screen->info, prsc->format, fd_resource_nr_samples(prsc),
prsc->width0, prsc->height0, prsc->depth0, prsc->last_level + 1,
prsc->array_size, prsc->target == PIPE_TEXTURE_3D, false, NULL);
prsc->array_size, prsc->target == PIPE_TEXTURE_3D, false, false, NULL);
if (!FD_DBG(NOLRZ) && has_depth(prsc->format) && !is_z32(prsc->format))
setup_lrz<CHIP>(rsc);
@ -282,7 +282,7 @@ fill_ubwc_buffer_sizes(struct fd_resource *rsc)
if (!fdl6_layout(&rsc->layout, screen->info, prsc->format, fd_resource_nr_samples(prsc),
prsc->width0, prsc->height0, prsc->depth0,
prsc->last_level + 1, prsc->array_size, false, false, &l))
prsc->last_level + 1, prsc->array_size, false, false, true, &l))
return -1;
if (rsc->layout.size > fd_bo_size(rsc->bo))