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freedreno,ir3: rename Z_CLAMP_ENABLE to Z_CLIP_DISABLE

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UNK5 of GRAS_CL_CNTL is still unclear though.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>
This commit is contained in:
Hyunjun Ko 2022-06-28 14:11:15 +09:00 • committed by Marge Bot
parent 0e7863c3b0
commit 6cb41c5188
6 changed files with 11 additions and 11 deletions
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2
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2128,7 +2128,7 @@ to upconvert to 32b float internally?
<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
<bitfield name="Z_CLIP_DISABLE" pos="5" type="boolean"/>
<doc>
Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
also set when Z_BOUNDS_ENABLE is set

2
src/freedreno/vulkan/tu_pipeline.c
View file

@ -3466,7 +3466,7 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder,
A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
if (rast_info->depthClampEnable)
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLIP_DISABLE;
if (ds_info->depthWriteEnable)
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;

8
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View file

@ -983,11 +983,11 @@ fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
.vert = guardband_y));
}
/* The clamp ranges are only used when the rasterizer wants depth
* clamping.
/* The clamp ranges are only used when the rasterizer disables
* depth clip.
*/
if ((dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER)) &&
fd_depth_clamp_enabled(ctx)) {
fd_depth_clip_disabled(ctx)) {
float zmin, zmax;
util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
&zmin, &zmax);
@ -1037,7 +1037,7 @@ fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
state = fd6_zsa_state(
ctx,
util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])),
fd_depth_clamp_enabled(ctx));
fd_depth_clip_disabled(ctx));
fd_ringbuffer_ref(state);
break;
case FD6_GROUP_LRZ:

4
src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
View file

@ -215,8 +215,8 @@ fd6_zsa_state_create(struct pipe_context *pctx,
OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
OUT_RING(ring,
so->rb_depth_cntl | COND(i & FD6_ZSA_DEPTH_CLAMP,
A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE));
so->rb_depth_cntl | COND(i & FD6_ZSA_DEPTH_CLIP_DISABLE,
A6XX_RB_DEPTH_CNTL_Z_CLIP_DISABLE));
OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
OUT_RING(ring, so->rb_stencilmask);

4
src/gallium/drivers/freedreno/a6xx/fd6_zsa.h
View file

@ -36,7 +36,7 @@
#include "fd6_context.h"
#define FD6_ZSA_NO_ALPHA (1 << 0)
#define FD6_ZSA_DEPTH_CLAMP (1 << 1)
#define FD6_ZSA_DEPTH_CLIP_DISABLE (1 << 1)
struct fd6_zsa_stateobj {
struct pipe_depth_stencil_alpha_state base;
@ -68,7 +68,7 @@ fd6_zsa_state(struct fd_context *ctx, bool no_alpha, bool depth_clamp) assert_dt
if (no_alpha)
variant |= FD6_ZSA_NO_ALPHA;
if (depth_clamp)
variant |= FD6_ZSA_DEPTH_CLAMP;
variant |= FD6_ZSA_DEPTH_CLIP_DISABLE;
return fd6_zsa_stateobj(ctx->zsa)->stateobj[variant];
}

2
src/gallium/drivers/freedreno/freedreno_state.h
View file

@ -55,7 +55,7 @@ fd_blend_enabled(struct fd_context *ctx, unsigned n) assert_dt
}
static inline bool
fd_depth_clamp_enabled(struct fd_context *ctx) assert_dt
fd_depth_clip_disabled(struct fd_context *ctx) assert_dt
{
return !(ctx->rasterizer->depth_clip_near &&
ctx->rasterizer->depth_clip_far);