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iris/gfx12.5: Pass non-empty push constant data to PS stage for TBIMR workaround.
Note that this bug leading to GPU hangs hasn't been reproduced on GL so far, workaround is mainly included for completeness. Fixes:57decad976("intel/xehp: Enable TBIMR by default.") Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30031> (cherry picked from commit49144ebcf9)
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3 changed files with 52 additions and 5 deletions
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@ -304,7 +304,7 @@
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"description": "iris/gfx12.5: Pass non-empty push constant data to PS stage for TBIMR workaround.",
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"nominated": true,
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"nomination_type": 1,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": "57decad9768a445de23d093cc8e004269a352b50",
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"notes": null
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@ -567,6 +567,8 @@ iris_to_brw_fs_key(const struct iris_screen *screen,
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.color_outputs_valid = key->color_outputs_valid,
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.input_slots_valid = key->input_slots_valid,
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.ignore_sample_mask_out = !key->multisample_fbo,
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.null_push_constant_tbimr_workaround =
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screen->devinfo->needs_null_push_constant_tbimr_workaround,
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};
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}
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@ -5186,7 +5186,8 @@ iris_store_fs_state(const struct intel_device_info *devinfo,
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devinfo->max_threads_per_psd - (GFX_VER == 8 ? 2 : 1);
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#if GFX_VER < 20
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ps.PushConstantEnable = shader->ubo_ranges[0].length > 0;
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ps.PushConstantEnable = devinfo->needs_null_push_constant_tbimr_workaround ||
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shader->ubo_ranges[0].length > 0;
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#endif
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/* From the documentation for this packet:
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@ -6395,6 +6396,42 @@ emit_push_constant_packets(struct iris_context *ice,
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}
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#if GFX_VER >= 12
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static void
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emit_null_push_constant_tbimr_workaround(struct iris_batch *batch)
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{
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struct isl_device *isl_dev = &batch->screen->isl_dev;
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/* Pass a single-register push constant payload for the PS
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* stage even if empty, since PS invocations with zero push
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* constant cycles have been found to cause hangs with TBIMR
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* enabled. See HSDES #22020184996.
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*
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* XXX - Use workaround infrastructure and final workaround
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* when provided by hardware team.
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*/
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const struct iris_address null_addr = {
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.bo = batch->screen->workaround_bo,
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.offset = 1024,
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};
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const uint32_t num_dwords = 2 + 2 * 1;
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uint32_t const_all[num_dwords];
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uint32_t *dw = &const_all[0];
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iris_pack_command(GENX(3DSTATE_CONSTANT_ALL), dw, all) {
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all.DWordLength = num_dwords - 2;
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all.MOCS = isl_mocs(isl_dev, 0, false);
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all.ShaderUpdateEnable = (1 << MESA_SHADER_FRAGMENT);
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all.PointerBufferMask = 1;
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}
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dw += 2;
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_iris_pack_state(batch, GENX(3DSTATE_CONSTANT_ALL_DATA), dw, data) {
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data.PointerToConstantBuffer = null_addr;
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data.ConstantBufferReadLength = 1;
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}
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iris_batch_emit(batch, const_all, sizeof(uint32_t) * num_dwords);
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}
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static void
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emit_push_constant_packet_all(struct iris_context *ice,
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struct iris_batch *batch,
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@ -6404,9 +6441,17 @@ emit_push_constant_packet_all(struct iris_context *ice,
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struct isl_device *isl_dev = &batch->screen->isl_dev;
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if (!push_bos) {
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iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_ALL), pc) {
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pc.ShaderUpdateEnable = shader_mask;
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pc.MOCS = iris_mocs(NULL, isl_dev, 0);
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if (batch->screen->devinfo->needs_null_push_constant_tbimr_workaround &&
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(shader_mask & (1 << MESA_SHADER_FRAGMENT))) {
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emit_null_push_constant_tbimr_workaround(batch);
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shader_mask &= ~(1 << MESA_SHADER_FRAGMENT);
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}
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if (shader_mask) {
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iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_ALL), pc) {
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pc.ShaderUpdateEnable = shader_mask;
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pc.MOCS = iris_mocs(NULL, isl_dev, 0);
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}
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}
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return;
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}
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