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intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11

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SML is no longer in the L3$ on Gen11+.  It's not incredibly clear from
the docs but no Gen11 platforms are in the list of platforms on which
this bit exists.  Also, we've been always setting it false on Gen11 in
ANV and i965 thanks to GEN_L3P_SLM being zero with no ill effects.

Cc: "20.0" mesa-stable@lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
(cherry picked from commit 73434b665b)
This commit is contained in:
Jason Ekstrand 2020-01-17 11:23:14 -06:00 • committed by Dylan Baker
parent ea7ab69455
commit 6c705ea125
5 changed files with 5 additions and 5 deletions
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2
.pick_status.json
View file

@ -229,7 +229,7 @@
"description": "intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": null
},

2
src/gallium/drivers/iris/iris_state.c
View file

@ -747,7 +747,7 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
#endif
iris_pack_state(L3_ALLOCATION_REG, &reg_val, reg) {
#if GEN_GEN < 12
#if GEN_GEN < 11
reg.SLMEnable = has_slm;
#endif
#if GEN_GEN == 11

1
src/intel/genxml/gen11.xml
View file

@ -6997,7 +6997,6 @@
</register>
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
<field name="Error Detection Behavior Control" start="9" end="9" type="bool"/>
<field name="Use Full Ways" start="10" end="10" type="bool"/>

2
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1889,7 +1889,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
uint32_t l3cr;
anv_pack_struct(&l3cr, L3_ALLOCATION_REG,
#if GEN_GEN < 12
#if GEN_GEN < 11
.SLMEnable = has_slm,
#endif
#if GEN_GEN == 11

3
src/mesa/drivers/dri/i965/gen7_l3_state.c
View file

@ -118,7 +118,8 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
if (devinfo->gen >= 8) {
assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
const unsigned imm_data = ((has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
const unsigned imm_data = (
(devinfo->gen < 11 && has_slm ? GEN8_L3CNTLREG_SLM_ENABLE : 0) |
(devinfo->gen == 11 ? GEN11_L3CNTLREG_USE_FULL_WAYS : 0) |
SET_FIELD(cfg->n[GEN_L3P_URB], GEN8_L3CNTLREG_URB_ALLOC) |
SET_FIELD(cfg->n[GEN_L3P_RO], GEN8_L3CNTLREG_RO_ALLOC) |