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vc4: Try to schedule QIR instructions between writing to and reading math.

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This helps us get the delay slots between SFU writes and reads filled.

total instructions in shared programs: 94494 -> 93970 (-0.55%)
instructions in affected programs:     59206 -> 58682 (-0.89%)

3DMMES performance +1.89967% +/- 0.157611% (n=10,9)
This commit is contained in:
Eric Anholt 2016-11-30 12:19:38 -08:00
parent d182740ac8
commit 6c34084d8e
1 changed files with 22 additions and 0 deletions
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22
src/gallium/drivers/vc4/vc4_qir_schedule.c
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@ -569,6 +569,28 @@ latency_between(struct schedule_node *before, struct schedule_node *after)
after->inst->op == QOP_TEX_RESULT)
return 100;
switch (before->inst->op) {
case QOP_RCP:
case QOP_RSQ:
case QOP_EXP2:
case QOP_LOG2:
for (int i = 0; i < qir_get_nsrc(after->inst); i++) {
if (after->inst->src[i].file ==
before->inst->dst.file &&
after->inst->src[i].index ==
before->inst->dst.index) {
/* There are two QPU delay slots before we can
* read a math result, which could be up to 4
* QIR instructions if they packed well.
*/
return 4;
}
}
break;
default:
break;
}
return 1;
}