aco: always emit vk_cvt_pkrtz_f16_f32 for nir_op_pack_half_2x16_split

From the VK_KHR_shader_float_controls extension:

    "5) Do any of the “Pack” GLSL.std.450 instructions count as
     conversion instructions and have the rounding mode applied?"

    "RESOLVED: No, only instructions listed in “section 3.32.11.
     Conversion Instructions” of the SPIR-V specification count as
     conversion instructions."

This is also the same logic as the LLVM backend.

No fossils-db changes on Sienna Cichlid.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15301>
This commit is contained in:
Samuel Pitoiset 2022-03-09 11:09:08 +01:00 committed by Marge Bot
parent fa41bd0687
commit 6c1c9067d9

View file

@ -3266,19 +3266,10 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
case nir_op_pack_32_4x8: bld.copy(Definition(dst), get_alu_src(ctx, instr->src[0], 4)); break;
case nir_op_pack_half_2x16_split: {
if (dst.regClass() == v1) {
if (!ctx->block->fp_mode.care_about_round16_64 ||
ctx->block->fp_mode.round16_64 == fp_round_tz) {
if (ctx->program->chip_class == GFX8 || ctx->program->chip_class == GFX9)
emit_vop3a_instruction(ctx, instr, aco_opcode::v_cvt_pkrtz_f16_f32_e64, dst);
else
emit_vop2_instruction(ctx, instr, aco_opcode::v_cvt_pkrtz_f16_f32, dst, false);
} else {
Temp src0 =
bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v2b), get_alu_src(ctx, instr->src[0]));
Temp src1 =
bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v2b), get_alu_src(ctx, instr->src[1]));
bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
}
if (ctx->program->chip_class == GFX8 || ctx->program->chip_class == GFX9)
emit_vop3a_instruction(ctx, instr, aco_opcode::v_cvt_pkrtz_f16_f32_e64, dst);
else
emit_vop2_instruction(ctx, instr, aco_opcode::v_cvt_pkrtz_f16_f32, dst, false);
} else {
isel_err(&instr->instr, "Unimplemented NIR instr bit size");
}