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i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets.

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The generator code ends up clearer this way than if we had to sniff
via the message length. Implemented via the gather4_po message in
hardware, which is present in Gen7 and later.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Chris Forbes 2013-10-08 21:42:10 +13:00
parent cd8505bfb8
commit 6bb2cf2107
6 changed files with 20 additions and 3 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -771,6 +771,7 @@ enum opcode {
SHADER_OPCODE_TXF_MS,
SHADER_OPCODE_LOD,
SHADER_OPCODE_TG4,
SHADER_OPCODE_TG4_OFFSET,
SHADER_OPCODE_SHADER_TIME_ADD,

1
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -756,6 +756,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:

8
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -438,6 +438,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
assert(brw->gen >= 6);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
break;
case SHADER_OPCODE_TG4_OFFSET:
assert(brw->gen >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
break;
default:
assert(!"not reached");
break;
@ -551,7 +555,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
}
}
uint32_t surface_index = (inst->opcode == SHADER_OPCODE_TG4
uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
inst->opcode == SHADER_OPCODE_TG4_OFFSET)
? c->prog_data.base.binding_table.gather_texture_start
: c->prog_data.base.binding_table.texture_start) + inst->sampler;
@ -1520,6 +1525,7 @@ fs_generator::generate_code(exec_list *instructions)
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
generate_tex(inst, dst, src[0]);
break;
case FS_OPCODE_DDX:

5
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -443,6 +443,8 @@ brw_instruction_name(enum opcode op)
return "txf_ms";
case SHADER_OPCODE_TG4:
return "tg4";
case SHADER_OPCODE_TG4_OFFSET:
return "tg4_offset";
case FS_OPCODE_DDX:
return "ddx";
@ -539,7 +541,8 @@ backend_instruction::is_tex()
opcode == SHADER_OPCODE_TXL ||
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD ||
opcode == SHADER_OPCODE_TG4);
opcode == SHADER_OPCODE_TG4 ||
opcode == SHADER_OPCODE_TG4_OFFSET);
}
bool

1
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -274,6 +274,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TXF_MS:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
return inst->header_present ? 1 : 0;
default:
assert(!"not reached");

7
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View file

@ -311,6 +311,9 @@ vec4_generator::generate_tex(vec4_instruction *inst,
case SHADER_OPCODE_TG4:
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
break;
case SHADER_OPCODE_TG4_OFFSET:
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
break;
default:
assert(!"should not get here: invalid VS texture opcode");
break;
@ -385,7 +388,8 @@ vec4_generator::generate_tex(vec4_instruction *inst,
break;
}
uint32_t surface_index = (inst->opcode == SHADER_OPCODE_TG4
uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
inst->opcode == SHADER_OPCODE_TG4_OFFSET)
? prog_data->base.binding_table.gather_texture_start
: prog_data->base.binding_table.texture_start) + inst->sampler;
@ -1096,6 +1100,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
generate_tex(inst, dst, src[0]);
break;