kk: Handle accurate OpSMod and default point size requirements

Reviewed-by: Arcady Goldmints-Orlov <arcady@lunarg.com>
Reviewed-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41663>
This commit is contained in:
squidbus 2026-05-16 15:56:00 -07:00 committed by Marge Bot
parent a512fec6b9
commit 6b6a8cbe67
4 changed files with 34 additions and 2 deletions

View file

@ -10,12 +10,18 @@ import sys
import math
a = 'a'
b = 'b'
lower_pack = [
lower = [
# Based on the VIR lowering
(('f2f16_rtz', 'a@32'),
('bcsel', ('flt', ('fabs', a), ('fabs', ('f2f32', ('f2f16_rtne', a)))),
('isub', ('f2f16_rtne', a), 1), ('f2f16_rtne', a))),
# Handle imod behavior with negative values using lowering
(('imod', a, b),
('bcsel', ('ior', ('ieq', ('irem', a, b), 0), ('ieq', ('isign', a), ('isign', b))),
('irem', a, b), ('iadd', ('irem', a, b), b))),
]
@ -32,7 +38,7 @@ def run():
print('#include "msl_private.h"')
print(nir_algebraic.AlgebraicPass("msl_nir_lower_algebraic_late", lower_pack).render())
print(nir_algebraic.AlgebraicPass("msl_nir_lower_algebraic_late", lower).render())
if __name__ == '__main__':
main()

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@ -242,6 +242,30 @@ msl_ensure_vertex_position_output(nir_shader *nir)
return false;
}
bool
msl_ensure_vertex_point_size_output(nir_shader *nir)
{
assert(nir->info.stage == MESA_SHADER_VERTEX);
bool has_point_size_write =
nir->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ);
if (!has_point_size_write) {
nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
nir_builder b = nir_builder_at(nir_before_impl(entrypoint));
struct nir_io_semantics io_semantics = {
.location = VARYING_SLOT_PSIZ,
.num_slots = 1u,
};
nir_store_output(&b, nir_imm_float(&b, 1.0f), nir_imm_int(&b, 0u),
.base = 0u, .range = 1u, .write_mask = 0x1, .component = 0u,
.src_type = nir_type_float32, .io_semantics = io_semantics);
nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_PSIZ);
}
return true;
}
static bool
msl_fs_io_types(nir_builder *b, nir_intrinsic_instr *intr, void *data)
{

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@ -72,6 +72,7 @@ bool msl_lower_textures(nir_shader *s);
bool msl_lower_static_sample_mask(nir_shader *nir, uint32_t sample_mask);
bool msl_ensure_depth_write(nir_shader *nir);
bool msl_ensure_vertex_position_output(nir_shader *nir);
bool msl_ensure_vertex_point_size_output(nir_shader *nir);
bool msl_nir_fs_io_types(nir_shader *nir);
bool msl_nir_vs_io_types(nir_shader *nir);
bool msl_nir_fake_guard_for_discards(struct nir_shader *nir);

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@ -503,6 +503,7 @@ kk_lower_nir(struct kk_device *dev, nir_shader *nir,
glsl_get_natural_size_align_bytes);
NIR_PASS(_, nir, msl_ensure_vertex_position_output);
NIR_PASS(_, nir, msl_ensure_vertex_point_size_output);
} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
NIR_PASS(_, nir, kk_nir_lower_fs_multiview, state->mv->view_mask);