From 6b6a4cb1e2d705889644e68c3ffe7d7f8f4256cb Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 20 Mar 2025 10:04:43 +0200 Subject: [PATCH] anv: fix end of pipe timestamp query writes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently trying to use PIPE_CONTROL on blitter/video engines. Signed-off-by: Lionel Landwerlin Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12833 Acked-by: Hyunjun Ko Reviewed-by: José Roberto de Souza Part-of: --- src/intel/vulkan/genX_query.c | 81 ++++++++++++++++++++++------------- 1 file changed, 52 insertions(+), 29 deletions(-) diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 3c46c901635..1652c491b4e 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -72,6 +72,51 @@ emit_query_mi_flush_availability(struct anv_cmd_buffer *cmd_buffer, } } +static void +emit_query_mi_availability(struct mi_builder *b, + struct anv_address addr, + bool available) +{ + mi_store(b, mi_mem64(addr), mi_imm(available)); +} + +static void +emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer, + struct anv_address addr, + bool available) +{ + cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT; + genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); + + genx_batch_emit_pipe_control_write + (&cmd_buffer->batch, cmd_buffer->device->info, + cmd_buffer->state.current_pipeline, WriteImmediateData, addr, + available, 0); +} + +/* End of pipe availability */ +static void +emit_query_eop_availability(struct anv_cmd_buffer *cmd_buffer, + struct anv_address addr, + bool available) +{ + switch (cmd_buffer->queue_family->engine_class) { + case INTEL_ENGINE_CLASS_RENDER: + case INTEL_ENGINE_CLASS_COMPUTE: + emit_query_pc_availability(cmd_buffer, addr, available); + break; + + case INTEL_ENGINE_CLASS_COPY: + case INTEL_ENGINE_CLASS_VIDEO: + case INTEL_ENGINE_CLASS_VIDEO_ENHANCE: + emit_query_mi_flush_availability(cmd_buffer, addr, available); + break; + + default: + unreachable("Invalid engine class"); + } +} + VkResult genX(CreateQueryPool)( VkDevice _device, const VkQueryPoolCreateInfo* pCreateInfo, @@ -728,28 +773,6 @@ emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer, ANV_PIPE_DEPTH_STALL_BIT | (cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0)); } -static void -emit_query_mi_availability(struct mi_builder *b, - struct anv_address addr, - bool available) -{ - mi_store(b, mi_mem64(addr), mi_imm(available)); -} - -static void -emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer, - struct anv_address addr, - bool available) -{ - cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT; - genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); - - genx_batch_emit_pipe_control_write - (&cmd_buffer->batch, cmd_buffer->device->info, - cmd_buffer->state.current_pipeline, WriteImmediateData, addr, - available, 0); -} - /** * Goes through a series of consecutive query indices in the given pool * setting all element values to 0 and emitting them as available. @@ -772,11 +795,11 @@ emit_zero_queries(struct anv_cmd_buffer *cmd_buffer, anv_query_address(pool, first_index + i); for (uint32_t qword = 1; qword < (pool->stride / 8); qword++) { - emit_query_pc_availability(cmd_buffer, - anv_address_add(slot_addr, qword * 8), - false); + emit_query_eop_availability(cmd_buffer, + anv_address_add(slot_addr, qword * 8), + false); } - emit_query_pc_availability(cmd_buffer, slot_addr, true); + emit_query_eop_availability(cmd_buffer, slot_addr, true); } break; @@ -878,9 +901,9 @@ void genX(CmdResetQueryPool)( case VK_QUERY_TYPE_TIMESTAMP: { for (uint32_t i = 0; i < queryCount; i++) { - emit_query_pc_availability(cmd_buffer, - anv_query_address(pool, firstQuery + i), - false); + emit_query_eop_availability(cmd_buffer, + anv_query_address(pool, firstQuery + i), + false); } /* Add a CS stall here to make sure the PIPE_CONTROL above has