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v3dv: DepthBiasEnable is dynamic now

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Since VK_EXT_extended_dynamic_state2

We just move all related with depth bias to the command buffer. There
is not good reason to compute and save it at the pipeline.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28980>
This commit is contained in:
Alejandro Piñeiro 2024-04-27 00:15:21 +02:00 • committed by Marge Bot
parent 8ab0c55a53
commit 6b59e1d8e4
5 changed files with 8 additions and 39 deletions
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3
src/broadcom/vulkan/v3dv_cmd_buffer.c
View file

@ -3007,7 +3007,8 @@ v3dv_cmd_buffer_emit_pre_draw(struct v3dv_cmd_buffer *cmd_buffer,
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_CULL_MODE) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_FRONT_FACE) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE)) {
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE)) {
v3dv_X(device, cmd_buffer_emit_configuration_bits)(cmd_buffer);
}

22
src/broadcom/vulkan/v3dv_pipeline.c
View file

@ -2663,26 +2663,6 @@ stencil_op_is_no_op(struct vk_stencil_test_face_state *stencil)
stencil->op.compare == VK_COMPARE_OP_ALWAYS;
}
static void
enable_depth_bias(struct v3dv_pipeline *pipeline,
const VkPipelineRasterizationStateCreateInfo *rs_info)
{
pipeline->depth_bias.enabled = false;
pipeline->depth_bias.is_z16 = false;
if (!rs_info || !rs_info->depthBiasEnable)
return;
/* Check the depth/stencil attachment description for the subpass used with
* this pipeline.
*/
VkFormat ds_format = pipeline->rendering_info.depth_attachment_format;
if (ds_format == VK_FORMAT_D16_UNORM)
pipeline->depth_bias.is_z16 = true;
pipeline->depth_bias.enabled = true;
}
/* Computes the ez_state based on a given vk_dynamic_graphics_state. Note
* that the parameter dyn doesn't need to be pipeline->dynamic_graphics_state,
* as this method can be used by the cmd_buffer too.
@ -2976,8 +2956,6 @@ pipeline_init(struct v3dv_pipeline *pipeline,
if (depth_clip_control)
pipeline->negative_one_to_one = depth_clip_control->negativeOneToOne;
enable_depth_bias(pipeline, rs_info);
v3dv_X(device, pipeline_pack_state)(pipeline, cb_info, ds_info,
rs_info, pv_info, ls_info,
ms_info,

6
src/broadcom/vulkan/v3dv_private.h
View file

@ -2348,12 +2348,6 @@ struct v3dv_pipeline {
uint32_t color_write_masks;
} blend;
/* Depth bias */
struct {
bool enabled;
bool is_z16;
} depth_bias;
struct {
void *mem_ctx;
struct util_dynarray data; /* Array of v3dv_pipeline_executable_data */

10
src/broadcom/vulkan/v3dvx_cmd_buffer.c
View file

@ -1501,15 +1501,14 @@ v3dX(cmd_buffer_emit_depth_bias)(struct v3dv_cmd_buffer *cmd_buffer)
{
struct v3dv_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
assert(pipeline);
struct vk_dynamic_graphics_state *dyn = &cmd_buffer->vk.dynamic_graphics_state;
if (!pipeline->depth_bias.enabled)
if (!dyn->rs.depth_bias.enable)
return;
struct v3dv_job *job = cmd_buffer->state.job;
assert(job);
struct vk_dynamic_graphics_state *dyn = &cmd_buffer->vk.dynamic_graphics_state;
v3dv_cl_ensure_space_with_branch(&job->bcl, cl_packet_length(DEPTH_OFFSET));
v3dv_return_if_oom(cmd_buffer, NULL);
@ -1517,7 +1516,7 @@ v3dX(cmd_buffer_emit_depth_bias)(struct v3dv_cmd_buffer *cmd_buffer)
bias.depth_offset_factor = dyn->rs.depth_bias.slope;
bias.depth_offset_units = dyn->rs.depth_bias.constant;
#if V3D_VERSION <= 42
if (pipeline->depth_bias.is_z16)
if (pipeline->rendering_info.depth_attachment_format == VK_FORMAT_D16_UNORM)
bias.depth_offset_units *= 256.0f;
#endif
bias.limit = dyn->rs.depth_bias.clamp;
@ -2029,12 +2028,15 @@ v3dX(cmd_buffer_emit_configuration_bits)(struct v3dv_cmd_buffer *cmd_buffer)
config.depth_bounds_test_enable =
dyn->ds.depth.bounds_test.enable && has_depth;
#endif
config.enable_depth_offset = dyn->rs.depth_bias.enable;
}
BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_RS_CULL_MODE);
BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_RS_FRONT_FACE);
BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_DS_DEPTH_BOUNDS_TEST_ENABLE);
BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_DS_STENCIL_TEST_ENABLE);
BITSET_CLEAR(dyn->dirty, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_ENABLE);
}
void

6
src/broadcom/vulkan/v3dvx_pipeline.c
View file

@ -151,12 +151,6 @@ pack_cfg_bits(struct v3dv_pipeline *pipeline,
ms_info && ms_info->rasterizationSamples > VK_SAMPLE_COUNT_1_BIT;
v3dvx_pack(pipeline->cfg_bits, CFG_BITS, config) {
/* Even if rs_info->depthBiasEnabled is true, we can decide to not
* enable it, like if there isn't a depth/stencil attachment with the
* pipeline.
*/
config.enable_depth_offset = pipeline->depth_bias.enabled;
/* This is required to pass line rasterization tests in CTS while
* exposing, at least, a minimum of 4-bits of subpixel precision
* (the minimum requirement).