mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 09:38:07 +02:00
radeonsi: move and rename scissor and viewport state and functions
v2: change GET_MAX_SCISSOR to SI_MAX_SCISSOR Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
parent
449ac258d1
commit
6b416ec3d6
10 changed files with 184 additions and 182 deletions
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@ -738,7 +738,6 @@ bool si_common_context_init(struct r600_common_context *rctx,
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rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
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si_init_context_texture_functions(rctx);
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si_init_viewport_functions(rctx);
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si_streamout_init(rctx);
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si_init_query_functions(rctx);
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si_init_msaa(&rctx->b);
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@ -120,7 +120,6 @@ struct u_log_context;
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#define DBG_NO_DFSM (1ull << 55)
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#define R600_MAP_BUFFER_ALIGNMENT 64
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#define R600_MAX_VIEWPORTS 16
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#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
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@ -523,27 +522,6 @@ struct r600_streamout {
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int num_prims_gen_queries;
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};
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struct r600_signed_scissor {
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int minx;
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int miny;
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int maxx;
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int maxy;
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};
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struct r600_scissors {
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struct r600_atom atom;
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unsigned dirty_mask;
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struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
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};
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struct r600_viewports {
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struct r600_atom atom;
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unsigned dirty_mask;
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unsigned depth_range_dirty_mask;
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struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
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struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
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};
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struct r600_ring {
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struct radeon_winsys_cs *cs;
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void (*flush)(void *ctx, unsigned flags,
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@ -590,12 +568,6 @@ struct r600_common_context {
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/* States. */
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struct r600_streamout streamout;
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struct r600_scissors scissors;
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struct r600_viewports viewports;
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bool scissor_enabled;
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bool clip_halfz;
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bool vs_writes_viewport_index;
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bool vs_disables_clipping_viewport;
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/* Additional context states. */
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unsigned flags; /* flush flags */
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@ -879,13 +851,6 @@ bool si_texture_disable_dcc(struct r600_common_context *rctx,
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void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
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void si_init_context_texture_functions(struct r600_common_context *rctx);
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/* r600_viewport.c */
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void si_viewport_set_rast_deps(struct r600_common_context *rctx,
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bool scissor_enable, bool clip_halfz);
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void si_update_vs_writes_viewport_index(struct r600_common_context *rctx,
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struct tgsi_shader_info *info);
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void si_init_viewport_functions(struct r600_common_context *rctx);
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/* cayman_msaa.c */
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void si_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
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unsigned sample_index, float *out_value);
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@ -70,8 +70,8 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
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util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);
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util_blitter_save_fragment_shader(sctx->blitter, sctx->ps_shader.cso);
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util_blitter_save_sample_mask(sctx->blitter, sctx->sample_mask.sample_mask);
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util_blitter_save_viewport(sctx->blitter, &sctx->b.viewports.states[0]);
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util_blitter_save_scissor(sctx->blitter, &sctx->b.scissors.states[0]);
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util_blitter_save_viewport(sctx->blitter, &sctx->viewports.states[0]);
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util_blitter_save_scissor(sctx->blitter, &sctx->scissors.states[0]);
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}
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if (op & SI_SAVE_FRAMEBUFFER)
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@ -248,11 +248,11 @@ void si_begin_new_cs(struct si_context *ctx)
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si_all_descriptors_begin_new_cs(ctx);
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si_all_resident_buffers_begin_new_cs(ctx);
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ctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
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ctx->b.viewports.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
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ctx->b.viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
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si_mark_atom_dirty(ctx, &ctx->b.scissors.atom);
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si_mark_atom_dirty(ctx, &ctx->b.viewports.atom);
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ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
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ctx->viewports.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
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ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
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si_mark_atom_dirty(ctx, &ctx->scissors.atom);
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si_mark_atom_dirty(ctx, &ctx->viewports.atom);
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si_mark_atom_dirty(ctx, &ctx->scratch_state);
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if (ctx->scratch_buffer) {
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@ -230,6 +230,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
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si_init_all_descriptors(sctx);
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si_init_state_functions(sctx);
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si_init_shader_functions(sctx);
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si_init_viewport_functions(sctx);
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si_init_ia_multi_vgt_param_table(sctx);
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if (sctx->b.chip_class >= CIK)
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@ -620,7 +621,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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/* Viewports and render targets. */
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case PIPE_CAP_MAX_VIEWPORTS:
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return R600_MAX_VIEWPORTS;
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return SI_MAX_VIEWPORTS;
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case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
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case PIPE_CAP_MAX_RENDER_TARGETS:
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return 8;
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@ -81,6 +81,7 @@
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#define SI_PREFETCH_PS (1 << 6)
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#define SI_MAX_BORDER_COLORS 4096
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#define SI_MAX_VIEWPORTS 16
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#define SIX_BITS 0x3F
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struct si_compute;
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@ -212,6 +213,27 @@ struct si_framebuffer {
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bool DB_has_shader_readable_metadata;
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};
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struct si_signed_scissor {
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int minx;
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int miny;
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int maxx;
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int maxy;
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};
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struct si_scissors {
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struct r600_atom atom;
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unsigned dirty_mask;
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struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
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};
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struct si_viewports {
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struct r600_atom atom;
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unsigned dirty_mask;
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unsigned depth_range_dirty_mask;
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struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
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struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
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};
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struct si_clip_state {
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struct r600_atom atom;
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struct pipe_clip_state state;
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@ -326,6 +348,8 @@ struct si_context {
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struct si_shader_data shader_pointers;
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struct si_stencil_ref stencil_ref;
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struct r600_atom spi_map;
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struct si_scissors scissors;
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struct si_viewports viewports;
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/* Precomputed states. */
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struct si_pm4_state *init_config;
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@ -437,6 +461,11 @@ struct si_context {
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bool need_check_render_feedback;
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bool decompression_enabled;
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bool scissor_enabled;
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bool clip_halfz;
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bool vs_writes_viewport_index;
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bool vs_disables_clipping_viewport;
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/* Precomputed IA_MULTI_VGT_PARAM */
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union si_vgt_param_key ia_multi_vgt_param_key;
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unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
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@ -536,6 +565,14 @@ struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
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struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
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const struct pipe_video_buffer *tmpl);
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/* si_viewport.c */
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void si_viewport_set_rast_deps(struct si_context *rctx,
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bool scissor_enable, bool clip_halfz);
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void si_update_vs_writes_viewport_index(struct si_context *ctx,
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struct tgsi_shader_info *info);
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void si_init_viewport_functions(struct si_context *ctx);
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/*
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* common helpers
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*/
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@ -1003,7 +1003,7 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
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sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
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sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
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si_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
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si_viewport_set_rast_deps(sctx, rs->scissor_enable, rs->clip_halfz);
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si_pm4_bind_state(sctx, rasterizer, rs);
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si_update_poly_offset_state(sctx);
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@ -4402,8 +4402,8 @@ void si_init_state_functions(struct si_context *sctx)
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si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
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si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
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si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
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si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
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si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
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si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
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si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
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si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
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si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
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@ -1261,8 +1261,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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bool old_is_poly = sctx->b.current_rast_prim >= PIPE_PRIM_TRIANGLES;
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bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
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if (old_is_poly != new_is_poly) {
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sctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
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si_set_atom_dirty(sctx, &sctx->b.scissors.atom, true);
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sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
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si_mark_atom_dirty(sctx, &sctx->scissors.atom);
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}
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sctx->b.current_rast_prim = rast_prim;
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@ -1398,7 +1398,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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* involved alternative workaround.
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*/
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if (sctx->b.chip_class == GFX9 &&
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si_is_atom_dirty(sctx, &sctx->b.scissors.atom)) {
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si_is_atom_dirty(sctx, &sctx->scissors.atom)) {
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sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
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si_emit_cache_flush(sctx);
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}
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@ -2301,7 +2301,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
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sctx->vs_shader.current = sel ? sel->first_variant : NULL;
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si_update_common_shader_state(sctx);
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si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
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si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
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si_set_active_descriptors_for_shader(sctx, sel);
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si_update_streamout_state(sctx);
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si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
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@ -2344,7 +2344,7 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
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if (sctx->ia_multi_vgt_param_key.u.uses_tess)
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si_update_tess_uses_prim_id(sctx);
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}
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si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
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si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
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si_set_active_descriptors_for_shader(sctx, sel);
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si_update_streamout_state(sctx);
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si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
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@ -2395,7 +2395,7 @@ static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
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si_shader_change_notify(sctx);
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sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
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}
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si_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
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si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
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si_set_active_descriptors_for_shader(sctx, sel);
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si_update_streamout_state(sctx);
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si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
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@ -21,36 +21,38 @@
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "si_pipe.h"
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#include "sid.h"
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#include "radeon/r600_cs.h"
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#include "util/u_viewport.h"
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#include "tgsi/tgsi_scan.h"
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#define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
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#define SI_MAX_SCISSOR 16384
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static void r600_set_scissor_states(struct pipe_context *ctx,
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unsigned start_slot,
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unsigned num_scissors,
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const struct pipe_scissor_state *state)
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static void si_set_scissor_states(struct pipe_context *pctx,
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unsigned start_slot,
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unsigned num_scissors,
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const struct pipe_scissor_state *state)
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{
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struct r600_common_context *rctx = (struct r600_common_context *)ctx;
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struct si_context *ctx = (struct si_context *)pctx;
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int i;
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for (i = 0; i < num_scissors; i++)
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rctx->scissors.states[start_slot + i] = state[i];
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ctx->scissors.states[start_slot + i] = state[i];
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if (!rctx->scissor_enabled)
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if (!ctx->scissor_enabled)
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return;
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rctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
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rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
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ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
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si_mark_atom_dirty(ctx, &ctx->scissors.atom);
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}
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/* Since the guard band disables clipping, we have to clip per-pixel
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* using a scissor.
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*/
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static void r600_get_scissor_from_viewport(struct r600_common_context *rctx,
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const struct pipe_viewport_state *vp,
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struct r600_signed_scissor *scissor)
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static void si_get_scissor_from_viewport(struct si_context *ctx,
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const struct pipe_viewport_state *vp,
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struct si_signed_scissor *scissor)
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{
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float tmp, minx, miny, maxx, maxy;
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@ -63,7 +65,7 @@ static void r600_get_scissor_from_viewport(struct r600_common_context *rctx,
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/* r600_draw_rectangle sets this. Disable the scissor. */
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if (minx == -1 && miny == -1 && maxx == 1 && maxy == 1) {
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scissor->minx = scissor->miny = 0;
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scissor->maxx = scissor->maxy = GET_MAX_SCISSOR(rctx);
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scissor->maxx = scissor->maxy = SI_MAX_SCISSOR;
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return;
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}
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@ -86,19 +88,18 @@ static void r600_get_scissor_from_viewport(struct r600_common_context *rctx,
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scissor->maxy = ceilf(maxy);
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}
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static void r600_clamp_scissor(struct r600_common_context *rctx,
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struct pipe_scissor_state *out,
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struct r600_signed_scissor *scissor)
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static void si_clamp_scissor(struct si_context *ctx,
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struct pipe_scissor_state *out,
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struct si_signed_scissor *scissor)
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{
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unsigned max_scissor = GET_MAX_SCISSOR(rctx);
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out->minx = CLAMP(scissor->minx, 0, max_scissor);
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out->miny = CLAMP(scissor->miny, 0, max_scissor);
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out->maxx = CLAMP(scissor->maxx, 0, max_scissor);
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out->maxy = CLAMP(scissor->maxy, 0, max_scissor);
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out->minx = CLAMP(scissor->minx, 0, SI_MAX_SCISSOR);
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out->miny = CLAMP(scissor->miny, 0, SI_MAX_SCISSOR);
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out->maxx = CLAMP(scissor->maxx, 0, SI_MAX_SCISSOR);
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out->maxy = CLAMP(scissor->maxy, 0, SI_MAX_SCISSOR);
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}
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static void r600_clip_scissor(struct pipe_scissor_state *out,
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struct pipe_scissor_state *clip)
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static void si_clip_scissor(struct pipe_scissor_state *out,
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struct pipe_scissor_state *clip)
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{
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out->minx = MAX2(out->minx, clip->minx);
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out->miny = MAX2(out->miny, clip->miny);
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@ -106,8 +107,8 @@ static void r600_clip_scissor(struct pipe_scissor_state *out,
|
|||
out->maxy = MIN2(out->maxy, clip->maxy);
|
||||
}
|
||||
|
||||
static void r600_scissor_make_union(struct r600_signed_scissor *out,
|
||||
struct r600_signed_scissor *in)
|
||||
static void si_scissor_make_union(struct si_signed_scissor *out,
|
||||
struct si_signed_scissor *in)
|
||||
{
|
||||
out->minx = MIN2(out->minx, in->minx);
|
||||
out->miny = MIN2(out->miny, in->miny);
|
||||
|
|
@ -115,22 +116,22 @@ static void r600_scissor_make_union(struct r600_signed_scissor *out,
|
|||
out->maxy = MAX2(out->maxy, in->maxy);
|
||||
}
|
||||
|
||||
static void r600_emit_one_scissor(struct r600_common_context *rctx,
|
||||
struct radeon_winsys_cs *cs,
|
||||
struct r600_signed_scissor *vp_scissor,
|
||||
struct pipe_scissor_state *scissor)
|
||||
static void si_emit_one_scissor(struct si_context *ctx,
|
||||
struct radeon_winsys_cs *cs,
|
||||
struct si_signed_scissor *vp_scissor,
|
||||
struct pipe_scissor_state *scissor)
|
||||
{
|
||||
struct pipe_scissor_state final;
|
||||
|
||||
if (rctx->vs_disables_clipping_viewport) {
|
||||
if (ctx->vs_disables_clipping_viewport) {
|
||||
final.minx = final.miny = 0;
|
||||
final.maxx = final.maxy = GET_MAX_SCISSOR(rctx);
|
||||
final.maxx = final.maxy = SI_MAX_SCISSOR;
|
||||
} else {
|
||||
r600_clamp_scissor(rctx, &final, vp_scissor);
|
||||
si_clamp_scissor(ctx, &final, vp_scissor);
|
||||
}
|
||||
|
||||
if (scissor)
|
||||
r600_clip_scissor(&final, scissor);
|
||||
si_clip_scissor(&final, scissor);
|
||||
|
||||
radeon_emit(cs, S_028250_TL_X(final.minx) |
|
||||
S_028250_TL_Y(final.miny) |
|
||||
|
|
@ -140,12 +141,12 @@ static void r600_emit_one_scissor(struct r600_common_context *rctx,
|
|||
}
|
||||
|
||||
/* the range is [-MAX, MAX] */
|
||||
#define GET_MAX_VIEWPORT_RANGE(rctx) (rctx->chip_class >= EVERGREEN ? 32768 : 16384)
|
||||
#define GET_MAX_VIEWPORT_RANGE(rctx) (32768)
|
||||
|
||||
static void r600_emit_guardband(struct r600_common_context *rctx,
|
||||
struct r600_signed_scissor *vp_as_scissor)
|
||||
static void si_emit_guardband(struct si_context *ctx,
|
||||
struct si_signed_scissor *vp_as_scissor)
|
||||
{
|
||||
struct radeon_winsys_cs *cs = rctx->gfx.cs;
|
||||
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
|
||||
struct pipe_viewport_state vp;
|
||||
float left, top, right, bottom, max_range, guardband_x, guardband_y;
|
||||
float discard_x, discard_y;
|
||||
|
|
@ -171,7 +172,7 @@ static void r600_emit_guardband(struct r600_common_context *rctx,
|
|||
*
|
||||
* Use a limit one pixel smaller to allow for some precision error.
|
||||
*/
|
||||
max_range = GET_MAX_VIEWPORT_RANGE(rctx) - 1;
|
||||
max_range = GET_MAX_VIEWPORT_RANGE(ctx) - 1;
|
||||
left = (-max_range - vp.translate[0]) / vp.scale[0];
|
||||
right = ( max_range - vp.translate[0]) / vp.scale[0];
|
||||
top = (-max_range - vp.translate[1]) / vp.scale[1];
|
||||
|
|
@ -185,7 +186,7 @@ static void r600_emit_guardband(struct r600_common_context *rctx,
|
|||
discard_x = 1.0;
|
||||
discard_y = 1.0;
|
||||
|
||||
if (rctx->current_rast_prim < PIPE_PRIM_TRIANGLES) {
|
||||
if (ctx->b.current_rast_prim < PIPE_PRIM_TRIANGLES) {
|
||||
/* When rendering wide points or lines, we need to be more
|
||||
* conservative about when to discard them entirely. Since
|
||||
* point size can be determined by the VS output, we basically
|
||||
|
|
@ -199,10 +200,7 @@ static void r600_emit_guardband(struct r600_common_context *rctx,
|
|||
}
|
||||
|
||||
/* If any of the GB registers is updated, all of them must be updated. */
|
||||
if (rctx->chip_class >= CAYMAN)
|
||||
radeon_set_context_reg_seq(cs, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
|
||||
else
|
||||
radeon_set_context_reg_seq(cs, R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
|
||||
radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
|
||||
|
||||
radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
|
||||
radeon_emit(cs, fui(discard_y)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
|
||||
|
|
@ -210,34 +208,35 @@ static void r600_emit_guardband(struct r600_common_context *rctx,
|
|||
radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
|
||||
}
|
||||
|
||||
static void r600_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom)
|
||||
static void si_emit_scissors(struct r600_common_context *rctx, struct r600_atom *atom)
|
||||
{
|
||||
struct radeon_winsys_cs *cs = rctx->gfx.cs;
|
||||
struct pipe_scissor_state *states = rctx->scissors.states;
|
||||
unsigned mask = rctx->scissors.dirty_mask;
|
||||
bool scissor_enabled = rctx->scissor_enabled;
|
||||
struct r600_signed_scissor max_vp_scissor;
|
||||
struct si_context *ctx = (struct si_context *)rctx;
|
||||
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
|
||||
struct pipe_scissor_state *states = ctx->scissors.states;
|
||||
unsigned mask = ctx->scissors.dirty_mask;
|
||||
bool scissor_enabled = ctx->scissor_enabled;
|
||||
struct si_signed_scissor max_vp_scissor;
|
||||
int i;
|
||||
|
||||
/* The simple case: Only 1 viewport is active. */
|
||||
if (!rctx->vs_writes_viewport_index) {
|
||||
struct r600_signed_scissor *vp = &rctx->viewports.as_scissor[0];
|
||||
if (!ctx->vs_writes_viewport_index) {
|
||||
struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
|
||||
|
||||
if (!(mask & 1))
|
||||
return;
|
||||
|
||||
radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
|
||||
r600_emit_one_scissor(rctx, cs, vp, scissor_enabled ? &states[0] : NULL);
|
||||
r600_emit_guardband(rctx, vp);
|
||||
rctx->scissors.dirty_mask &= ~1; /* clear one bit */
|
||||
si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
|
||||
si_emit_guardband(ctx, vp);
|
||||
ctx->scissors.dirty_mask &= ~1; /* clear one bit */
|
||||
return;
|
||||
}
|
||||
|
||||
/* Shaders can draw to any viewport. Make a union of all viewports. */
|
||||
max_vp_scissor = rctx->viewports.as_scissor[0];
|
||||
for (i = 1; i < R600_MAX_VIEWPORTS; i++)
|
||||
r600_scissor_make_union(&max_vp_scissor,
|
||||
&rctx->viewports.as_scissor[i]);
|
||||
max_vp_scissor = ctx->viewports.as_scissor[0];
|
||||
for (i = 1; i < SI_MAX_VIEWPORTS; i++)
|
||||
si_scissor_make_union(&max_vp_scissor,
|
||||
&ctx->viewports.as_scissor[i]);
|
||||
|
||||
while (mask) {
|
||||
int start, count, i;
|
||||
|
|
@ -247,43 +246,43 @@ static void r600_emit_scissors(struct r600_common_context *rctx, struct r600_ato
|
|||
radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
|
||||
start * 4 * 2, count * 2);
|
||||
for (i = start; i < start+count; i++) {
|
||||
r600_emit_one_scissor(rctx, cs, &rctx->viewports.as_scissor[i],
|
||||
scissor_enabled ? &states[i] : NULL);
|
||||
si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
|
||||
scissor_enabled ? &states[i] : NULL);
|
||||
}
|
||||
}
|
||||
r600_emit_guardband(rctx, &max_vp_scissor);
|
||||
rctx->scissors.dirty_mask = 0;
|
||||
si_emit_guardband(ctx, &max_vp_scissor);
|
||||
ctx->scissors.dirty_mask = 0;
|
||||
}
|
||||
|
||||
static void r600_set_viewport_states(struct pipe_context *ctx,
|
||||
unsigned start_slot,
|
||||
unsigned num_viewports,
|
||||
const struct pipe_viewport_state *state)
|
||||
static void si_set_viewport_states(struct pipe_context *pctx,
|
||||
unsigned start_slot,
|
||||
unsigned num_viewports,
|
||||
const struct pipe_viewport_state *state)
|
||||
{
|
||||
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
|
||||
struct si_context *ctx = (struct si_context *)pctx;
|
||||
unsigned mask;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_viewports; i++) {
|
||||
unsigned index = start_slot + i;
|
||||
|
||||
rctx->viewports.states[index] = state[i];
|
||||
r600_get_scissor_from_viewport(rctx, &state[i],
|
||||
&rctx->viewports.as_scissor[index]);
|
||||
ctx->viewports.states[index] = state[i];
|
||||
si_get_scissor_from_viewport(ctx, &state[i],
|
||||
&ctx->viewports.as_scissor[index]);
|
||||
}
|
||||
|
||||
mask = ((1 << num_viewports) - 1) << start_slot;
|
||||
rctx->viewports.dirty_mask |= mask;
|
||||
rctx->viewports.depth_range_dirty_mask |= mask;
|
||||
rctx->scissors.dirty_mask |= mask;
|
||||
rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
|
||||
rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
|
||||
ctx->viewports.dirty_mask |= mask;
|
||||
ctx->viewports.depth_range_dirty_mask |= mask;
|
||||
ctx->scissors.dirty_mask |= mask;
|
||||
si_mark_atom_dirty(ctx, &ctx->viewports.atom);
|
||||
si_mark_atom_dirty(ctx, &ctx->scissors.atom);
|
||||
}
|
||||
|
||||
static void r600_emit_one_viewport(struct r600_common_context *rctx,
|
||||
struct pipe_viewport_state *state)
|
||||
static void si_emit_one_viewport(struct si_context *ctx,
|
||||
struct pipe_viewport_state *state)
|
||||
{
|
||||
struct radeon_winsys_cs *cs = rctx->gfx.cs;
|
||||
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
|
||||
|
||||
radeon_emit(cs, fui(state->scale[0]));
|
||||
radeon_emit(cs, fui(state->translate[0]));
|
||||
|
|
@ -293,20 +292,20 @@ static void r600_emit_one_viewport(struct r600_common_context *rctx,
|
|||
radeon_emit(cs, fui(state->translate[2]));
|
||||
}
|
||||
|
||||
static void r600_emit_viewports(struct r600_common_context *rctx)
|
||||
static void si_emit_viewports(struct si_context *ctx)
|
||||
{
|
||||
struct radeon_winsys_cs *cs = rctx->gfx.cs;
|
||||
struct pipe_viewport_state *states = rctx->viewports.states;
|
||||
unsigned mask = rctx->viewports.dirty_mask;
|
||||
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
|
||||
struct pipe_viewport_state *states = ctx->viewports.states;
|
||||
unsigned mask = ctx->viewports.dirty_mask;
|
||||
|
||||
/* The simple case: Only 1 viewport is active. */
|
||||
if (!rctx->vs_writes_viewport_index) {
|
||||
if (!ctx->vs_writes_viewport_index) {
|
||||
if (!(mask & 1))
|
||||
return;
|
||||
|
||||
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
|
||||
r600_emit_one_viewport(rctx, &states[0]);
|
||||
rctx->viewports.dirty_mask &= ~1; /* clear one bit */
|
||||
si_emit_one_viewport(ctx, &states[0]);
|
||||
ctx->viewports.dirty_mask &= ~1; /* clear one bit */
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -318,29 +317,29 @@ static void r600_emit_viewports(struct r600_common_context *rctx)
|
|||
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
|
||||
start * 4 * 6, count * 6);
|
||||
for (i = start; i < start+count; i++)
|
||||
r600_emit_one_viewport(rctx, &states[i]);
|
||||
si_emit_one_viewport(ctx, &states[i]);
|
||||
}
|
||||
rctx->viewports.dirty_mask = 0;
|
||||
ctx->viewports.dirty_mask = 0;
|
||||
}
|
||||
|
||||
static void r600_emit_depth_ranges(struct r600_common_context *rctx)
|
||||
static void si_emit_depth_ranges(struct si_context *ctx)
|
||||
{
|
||||
struct radeon_winsys_cs *cs = rctx->gfx.cs;
|
||||
struct pipe_viewport_state *states = rctx->viewports.states;
|
||||
unsigned mask = rctx->viewports.depth_range_dirty_mask;
|
||||
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
|
||||
struct pipe_viewport_state *states = ctx->viewports.states;
|
||||
unsigned mask = ctx->viewports.depth_range_dirty_mask;
|
||||
float zmin, zmax;
|
||||
|
||||
/* The simple case: Only 1 viewport is active. */
|
||||
if (!rctx->vs_writes_viewport_index) {
|
||||
if (!ctx->vs_writes_viewport_index) {
|
||||
if (!(mask & 1))
|
||||
return;
|
||||
|
||||
util_viewport_zmin_zmax(&states[0], rctx->clip_halfz, &zmin, &zmax);
|
||||
util_viewport_zmin_zmax(&states[0], ctx->clip_halfz, &zmin, &zmax);
|
||||
|
||||
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
|
||||
radeon_emit(cs, fui(zmin));
|
||||
radeon_emit(cs, fui(zmax));
|
||||
rctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
|
||||
ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -352,34 +351,35 @@ static void r600_emit_depth_ranges(struct r600_common_context *rctx)
|
|||
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
|
||||
start * 4 * 2, count * 2);
|
||||
for (i = start; i < start+count; i++) {
|
||||
util_viewport_zmin_zmax(&states[i], rctx->clip_halfz, &zmin, &zmax);
|
||||
util_viewport_zmin_zmax(&states[i], ctx->clip_halfz, &zmin, &zmax);
|
||||
radeon_emit(cs, fui(zmin));
|
||||
radeon_emit(cs, fui(zmax));
|
||||
}
|
||||
}
|
||||
rctx->viewports.depth_range_dirty_mask = 0;
|
||||
ctx->viewports.depth_range_dirty_mask = 0;
|
||||
}
|
||||
|
||||
static void r600_emit_viewport_states(struct r600_common_context *rctx,
|
||||
struct r600_atom *atom)
|
||||
static void si_emit_viewport_states(struct r600_common_context *rctx,
|
||||
struct r600_atom *atom)
|
||||
{
|
||||
r600_emit_viewports(rctx);
|
||||
r600_emit_depth_ranges(rctx);
|
||||
struct si_context *ctx = (struct si_context *)rctx;
|
||||
si_emit_viewports(ctx);
|
||||
si_emit_depth_ranges(ctx);
|
||||
}
|
||||
|
||||
/* Set viewport dependencies on pipe_rasterizer_state. */
|
||||
void si_viewport_set_rast_deps(struct r600_common_context *rctx,
|
||||
void si_viewport_set_rast_deps(struct si_context *ctx,
|
||||
bool scissor_enable, bool clip_halfz)
|
||||
{
|
||||
if (rctx->scissor_enabled != scissor_enable) {
|
||||
rctx->scissor_enabled = scissor_enable;
|
||||
rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
|
||||
rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
|
||||
if (ctx->scissor_enabled != scissor_enable) {
|
||||
ctx->scissor_enabled = scissor_enable;
|
||||
ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
|
||||
si_mark_atom_dirty(ctx, &ctx->scissors.atom);
|
||||
}
|
||||
if (rctx->clip_halfz != clip_halfz) {
|
||||
rctx->clip_halfz = clip_halfz;
|
||||
rctx->viewports.depth_range_dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
|
||||
rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
|
||||
if (ctx->clip_halfz != clip_halfz) {
|
||||
ctx->clip_halfz = clip_halfz;
|
||||
ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
|
||||
si_mark_atom_dirty(ctx, &ctx->viewports.atom);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -389,7 +389,7 @@ void si_viewport_set_rast_deps(struct r600_common_context *rctx,
|
|||
* is delayed. When a shader with VIEWPORT_INDEX appears, this should be
|
||||
* called to emit the rest.
|
||||
*/
|
||||
void si_update_vs_writes_viewport_index(struct r600_common_context *rctx,
|
||||
void si_update_vs_writes_viewport_index(struct si_context *ctx,
|
||||
struct tgsi_shader_info *info)
|
||||
{
|
||||
bool vs_window_space;
|
||||
|
|
@ -401,33 +401,33 @@ void si_update_vs_writes_viewport_index(struct r600_common_context *rctx,
|
|||
vs_window_space =
|
||||
info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
|
||||
|
||||
if (rctx->vs_disables_clipping_viewport != vs_window_space) {
|
||||
rctx->vs_disables_clipping_viewport = vs_window_space;
|
||||
rctx->scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS) - 1;
|
||||
rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
|
||||
if (ctx->vs_disables_clipping_viewport != vs_window_space) {
|
||||
ctx->vs_disables_clipping_viewport = vs_window_space;
|
||||
ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
|
||||
si_mark_atom_dirty(ctx, &ctx->scissors.atom);
|
||||
}
|
||||
|
||||
/* Viewport index handling. */
|
||||
rctx->vs_writes_viewport_index = info->writes_viewport_index;
|
||||
if (!rctx->vs_writes_viewport_index)
|
||||
ctx->vs_writes_viewport_index = info->writes_viewport_index;
|
||||
if (!ctx->vs_writes_viewport_index)
|
||||
return;
|
||||
|
||||
if (rctx->scissors.dirty_mask)
|
||||
rctx->set_atom_dirty(rctx, &rctx->scissors.atom, true);
|
||||
if (ctx->scissors.dirty_mask)
|
||||
si_mark_atom_dirty(ctx, &ctx->scissors.atom);
|
||||
|
||||
if (rctx->viewports.dirty_mask ||
|
||||
rctx->viewports.depth_range_dirty_mask)
|
||||
rctx->set_atom_dirty(rctx, &rctx->viewports.atom, true);
|
||||
if (ctx->viewports.dirty_mask ||
|
||||
ctx->viewports.depth_range_dirty_mask)
|
||||
si_mark_atom_dirty(ctx, &ctx->viewports.atom);
|
||||
}
|
||||
|
||||
void si_init_viewport_functions(struct r600_common_context *rctx)
|
||||
void si_init_viewport_functions(struct si_context *ctx)
|
||||
{
|
||||
rctx->scissors.atom.emit = r600_emit_scissors;
|
||||
rctx->viewports.atom.emit = r600_emit_viewport_states;
|
||||
ctx->scissors.atom.emit = si_emit_scissors;
|
||||
ctx->viewports.atom.emit = si_emit_viewport_states;
|
||||
|
||||
rctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
|
||||
rctx->viewports.atom.num_dw = 2 + 16 * 6;
|
||||
ctx->scissors.atom.num_dw = (2 + 16 * 2) + 6;
|
||||
ctx->viewports.atom.num_dw = 2 + 16 * 6;
|
||||
|
||||
rctx->b.set_scissor_states = r600_set_scissor_states;
|
||||
rctx->b.set_viewport_states = r600_set_viewport_states;
|
||||
ctx->b.b.set_scissor_states = si_set_scissor_states;
|
||||
ctx->b.b.set_viewport_states = si_set_viewport_states;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue