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panvk: Transition the graphics pipeline logic to vk_graphics_pipeline_state
Fill a vk_graphics_pipeline_state and pass it around instead of passing VkGraphicsPipelineCreateInfo. We also call vk_cmd_set_dynamic_graphics_state() from CmdBindPipeline() to prepare for a smooth 'make it all dynamic' transition. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28927>
This commit is contained in:
Boris Brezillon
Marge Bot
parent
160db68bd7
commit
6b1a8226fa
4 changed files with 180 additions and 194 deletions
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@ -113,6 +113,11 @@ struct panvk_cmd_graphics_state {
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struct panvk_descriptor_state desc_state;
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const struct panvk_graphics_pipeline *pipeline;
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struct {
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struct vk_vertex_input_state vi;
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struct vk_sample_locations_state sl;
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} dynamic;
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uint32_t dirty;
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struct panvk_graphics_sysvals sysvals;
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@ -13,6 +13,7 @@
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#include <stdbool.h>
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#include <stdint.h>
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#include "vk_graphics_state.h"
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#include "vk_object.h"
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#include "util/pan_ir.h"
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@ -151,6 +152,11 @@ struct panvk_graphics_pipeline {
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VkViewport viewport;
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VkRect2D scissor;
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} vp;
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struct vk_dynamic_graphics_state dynamic;
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struct vk_vertex_input_state vi;
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struct vk_sample_locations_state sl;
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struct vk_render_pass_state rp;
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} state;
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};
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@ -1637,6 +1637,10 @@ panvk_create_cmdbuf(struct vk_command_pool *vk_pool, VkCommandBufferLevel level,
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return result;
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}
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cmdbuf->vk.dynamic_graphics_state.vi = &cmdbuf->state.gfx.dynamic.vi;
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cmdbuf->vk.dynamic_graphics_state.ms.sample_locations =
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&cmdbuf->state.gfx.dynamic.sl;
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panvk_pool_init(&cmdbuf->desc_pool, device, &pool->desc_bo_pool, 0,
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64 * 1024, "Command buffer descriptor pool", true);
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panvk_pool_init(
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@ -2122,6 +2126,9 @@ panvk_per_arch(CmdBindPipeline)(VkCommandBuffer commandBuffer,
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struct panvk_graphics_pipeline *gfx_pipeline =
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panvk_pipeline_to_graphics_pipeline(pipeline);
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vk_cmd_set_dynamic_graphics_state(&cmdbuf->vk,
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&gfx_pipeline->state.dynamic);
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cmdbuf->state.gfx.fs_rsd = 0;
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cmdbuf->state.gfx.varyings = gfx_pipeline->varyings;
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@ -67,12 +67,12 @@ release_shaders(struct panvk_pipeline *pipeline, struct panvk_shader **shaders,
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}
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static bool
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is_static_state(const struct panvk_graphics_pipeline *pipeline, uint32_t id)
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dyn_state_is_set(const struct panvk_graphics_pipeline *pipeline, uint32_t id)
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{
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if (!pipeline)
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return false;
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return !(pipeline->state.dynamic_mask & (1 << id));
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return BITSET_TEST(pipeline->state.dynamic.set, id);
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}
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static VkResult
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@ -105,7 +105,7 @@ compile_shaders(struct panvk_pipeline *pipeline,
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shader = panvk_per_arch(shader_create)(
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dev, stage, stage_info, pipeline->layout,
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gfx_pipeline ? &gfx_pipeline->state.blend.pstate : NULL,
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is_static_state(gfx_pipeline, VK_DYNAMIC_STATE_BLEND_CONSTANTS),
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dyn_state_is_set(gfx_pipeline, MESA_VK_DYNAMIC_CB_BLEND_CONSTANTS),
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alloc);
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if (!shader)
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return VK_ERROR_OUT_OF_HOST_MEMORY;
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@ -204,26 +204,26 @@ emit_base_fs_rsd(const struct panvk_graphics_pipeline *pipeline, void *rsd)
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cfg.stencil_mask_misc.single_sampled_lines =
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pipeline->state.ms.rast_samples <= 1;
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if (is_static_state(pipeline, VK_DYNAMIC_STATE_DEPTH_BIAS)) {
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if (dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_RS_DEPTH_BIAS_FACTORS)) {
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cfg.depth_units =
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pipeline->state.rast.depth_bias.constant_factor * 2.0f;
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cfg.depth_factor = pipeline->state.rast.depth_bias.slope_factor;
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cfg.depth_bias_clamp = pipeline->state.rast.depth_bias.clamp;
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}
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if (is_static_state(pipeline, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
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if (dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_DS_STENCIL_COMPARE_MASK)) {
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cfg.stencil_front.mask = pipeline->state.zs.s_front.compare_mask;
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cfg.stencil_back.mask = pipeline->state.zs.s_back.compare_mask;
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}
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if (is_static_state(pipeline, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
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if (dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_DS_STENCIL_WRITE_MASK)) {
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cfg.stencil_mask_misc.stencil_mask_front =
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pipeline->state.zs.s_front.write_mask;
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cfg.stencil_mask_misc.stencil_mask_back =
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pipeline->state.zs.s_back.write_mask;
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}
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if (is_static_state(pipeline, VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
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if (dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_DS_STENCIL_REFERENCE)) {
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cfg.stencil_front.reference_value = pipeline->state.zs.s_front.ref;
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cfg.stencil_back.reference_value = pipeline->state.zs.s_back.ref;
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}
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@ -400,55 +400,59 @@ init_shaders(struct panvk_pipeline *pipeline,
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static void
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parse_viewport(struct panvk_graphics_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *create_info)
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const struct vk_graphics_pipeline_state *state)
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{
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const struct vk_rasterization_state *rs = state->rs;
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const struct vk_viewport_state *vp = state->vp;
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/* The spec says:
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*
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* pViewportState is a pointer to an instance of the
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* VkPipelineViewportStateCreateInfo structure, and is ignored if the
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* pipeline has rasterization disabled.
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*/
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if (!create_info->pRasterizationState->rasterizerDiscardEnable &&
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is_static_state(pipeline, VK_DYNAMIC_STATE_VIEWPORT) &&
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is_static_state(pipeline, VK_DYNAMIC_STATE_SCISSOR)) {
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if (!rs->rasterizer_discard_enable &&
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dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_VP_VIEWPORTS) &&
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dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_VP_SCISSORS)) {
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struct panfrost_ptr vpd =
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pan_pool_alloc_desc(&pipeline->base.desc_pool.base, VIEWPORT);
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panvk_per_arch(emit_viewport)(create_info->pViewportState->pViewports,
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create_info->pViewportState->pScissors,
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vpd.cpu);
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panvk_per_arch(emit_viewport)(vp->viewports, vp->scissors, vpd.cpu);
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pipeline->state.vp.vpd = vpd.gpu;
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}
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if (is_static_state(pipeline, VK_DYNAMIC_STATE_VIEWPORT) &&
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create_info->pViewportState)
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pipeline->state.vp.viewport = create_info->pViewportState->pViewports[0];
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if (dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_VP_VIEWPORTS))
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pipeline->state.vp.viewport = vp->viewports[0];
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if (is_static_state(pipeline, VK_DYNAMIC_STATE_SCISSOR) &&
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create_info->pViewportState)
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pipeline->state.vp.scissor = create_info->pViewportState->pScissors[0];
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if (dyn_state_is_set(pipeline, MESA_VK_DYNAMIC_VP_SCISSORS))
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pipeline->state.vp.scissor = vp->scissors[0];
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}
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#define is_dyn(__state, __name) \
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BITSET_TEST((__state)->dynamic, MESA_VK_DYNAMIC_##__name)
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static void
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parse_dynamic_state(struct panvk_graphics_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *create_info)
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const struct vk_graphics_pipeline_state *state)
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{
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const VkPipelineDynamicStateCreateInfo *dynamic_info =
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create_info->pDynamicState;
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if (!dynamic_info)
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return;
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for (uint32_t i = 0; i < dynamic_info->dynamicStateCount; i++) {
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VkDynamicState state = dynamic_info->pDynamicStates[i];
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switch (state) {
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case VK_DYNAMIC_STATE_VIEWPORT ... VK_DYNAMIC_STATE_STENCIL_REFERENCE:
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pipeline->state.dynamic_mask |= 1 << state;
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break;
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default:
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unreachable("unsupported dynamic state");
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}
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}
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if (is_dyn(state, VP_VIEWPORTS))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_VIEWPORT;
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if (is_dyn(state, VP_SCISSORS))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_SCISSOR;
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if (is_dyn(state, RS_LINE_WIDTH))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_LINE_WIDTH;
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if (is_dyn(state, RS_DEPTH_BIAS_FACTORS))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_DEPTH_BIAS;
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if (is_dyn(state, CB_BLEND_CONSTANTS))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_BLEND_CONSTANTS;
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if (is_dyn(state, DS_DEPTH_BOUNDS_TEST_BOUNDS))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_DEPTH_BOUNDS;
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if (is_dyn(state, DS_STENCIL_COMPARE_MASK))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_STENCIL_COMPARE_MASK;
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if (is_dyn(state, DS_STENCIL_WRITE_MASK))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_STENCIL_WRITE_MASK;
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if (is_dyn(state, DS_STENCIL_REFERENCE))
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pipeline->state.dynamic_mask |= PANVK_DYNAMIC_STENCIL_REFERENCE;
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}
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static enum mali_draw_mode
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@ -479,84 +483,69 @@ translate_prim_topology(VkPrimitiveTopology in)
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static void
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parse_input_assembly(struct panvk_graphics_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *create_info)
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const struct vk_graphics_pipeline_state *state)
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{
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pipeline->state.ia.primitive_restart =
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create_info->pInputAssemblyState->primitiveRestartEnable;
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const struct vk_input_assembly_state *ia = state->ia;
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pipeline->state.ia.primitive_restart = ia->primitive_restart_enable;
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pipeline->state.ia.topology =
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translate_prim_topology(create_info->pInputAssemblyState->topology);
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translate_prim_topology(ia->primitive_topology);
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}
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static uint32_t
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get_active_color_attachments(const VkGraphicsPipelineCreateInfo *create_info,
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enum pipe_format *attachment_formats)
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get_active_color_attachments(const struct vk_graphics_pipeline_state *state)
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{
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if (create_info->pRasterizationState->rasterizerDiscardEnable)
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const struct vk_color_blend_state *cb = state->cb;
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if (state->rs->rasterizer_discard_enable || !cb)
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return 0;
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VK_FROM_HANDLE(vk_render_pass, pass, create_info->renderPass);
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const struct vk_subpass *subpass = &pass->subpasses[create_info->subpass];
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uint32_t active_color_attachments = 0;
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for (uint32_t i = 0; i < subpass->color_count; i++) {
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uint32_t idx = subpass->color_attachments[i].attachment;
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if (idx == VK_ATTACHMENT_UNUSED)
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continue;
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active_color_attachments |= 1 << i;
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if (attachment_formats)
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attachment_formats[i] =
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vk_format_to_pipe_format(pass->attachments[idx].format);
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}
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return active_color_attachments;
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return cb->color_write_enables & BITFIELD_MASK(cb->attachment_count);
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}
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static void
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parse_color_blend(struct panvk_graphics_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *create_info)
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const struct vk_graphics_pipeline_state *state)
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{
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if (!create_info->pColorBlendState)
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return;
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enum pipe_format attachment_formats[MAX_RTS] = {0};
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unsigned active_color_attachments =
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get_active_color_attachments(create_info, attachment_formats);
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const struct vk_color_blend_state *cb = state->cb;
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const struct vk_render_pass_state *rp = state->rp;
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const struct vk_multisample_state *ms = state->ms;
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struct panvk_device *dev = to_panvk_device(pipeline->base.base.device);
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pipeline->state.blend.pstate.logicop_enable =
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create_info->pColorBlendState->logicOpEnable;
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if (!cb)
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return;
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uint32_t active_color_attachments = get_active_color_attachments(state);
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pipeline->state.blend.pstate.logicop_enable = cb->logic_op_enable;
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pipeline->state.blend.pstate.logicop_func =
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vk_logic_op_to_pipe(create_info->pColorBlendState->logicOp);
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vk_logic_op_to_pipe(cb->logic_op);
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pipeline->state.blend.pstate.rt_count =
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util_last_bit(active_color_attachments);
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memcpy(pipeline->state.blend.pstate.constants,
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create_info->pColorBlendState->blendConstants,
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memcpy(pipeline->state.blend.pstate.constants, cb->blend_constants,
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sizeof(pipeline->state.blend.pstate.constants));
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for (unsigned i = 0; i < pipeline->state.blend.pstate.rt_count; i++) {
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const VkPipelineColorBlendAttachmentState *in =
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&create_info->pColorBlendState->pAttachments[i];
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const struct vk_color_blend_attachment_state *in = &cb->attachments[i];
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struct pan_blend_rt_state *out = &pipeline->state.blend.pstate.rts[i];
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out->format = attachment_formats[i];
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out->format = vk_format_to_pipe_format(rp->color_attachment_formats[i]);
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bool dest_has_alpha = util_format_has_alpha(out->format);
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out->nr_samples = create_info->pMultisampleState->rasterizationSamples;
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out->equation.blend_enable = in->blendEnable;
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out->equation.color_mask = in->colorWriteMask;
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out->equation.rgb_func = vk_blend_op_to_pipe(in->colorBlendOp);
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out->nr_samples = ms->rasterization_samples;
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out->equation.blend_enable = in->blend_enable;
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out->equation.color_mask = in->write_mask;
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out->equation.rgb_func = vk_blend_op_to_pipe(in->color_blend_op);
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out->equation.rgb_src_factor =
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vk_blend_factor_to_pipe(in->srcColorBlendFactor);
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vk_blend_factor_to_pipe(in->src_color_blend_factor);
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out->equation.rgb_dst_factor =
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vk_blend_factor_to_pipe(in->dstColorBlendFactor);
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out->equation.alpha_func = vk_blend_op_to_pipe(in->alphaBlendOp);
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vk_blend_factor_to_pipe(in->dst_color_blend_factor);
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out->equation.alpha_func = vk_blend_op_to_pipe(in->alpha_blend_op);
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out->equation.alpha_src_factor =
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vk_blend_factor_to_pipe(in->srcAlphaBlendFactor);
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vk_blend_factor_to_pipe(in->src_alpha_blend_factor);
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out->equation.alpha_dst_factor =
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vk_blend_factor_to_pipe(in->dstAlphaBlendFactor);
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vk_blend_factor_to_pipe(in->dst_alpha_blend_factor);
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if (!dest_has_alpha) {
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out->equation.rgb_src_factor =
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@ -598,19 +587,19 @@ parse_color_blend(struct panvk_graphics_pipeline *pipeline,
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static void
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parse_multisample(struct panvk_graphics_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *create_info)
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const struct vk_graphics_pipeline_state *state)
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{
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unsigned nr_samples =
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MAX2(create_info->pMultisampleState->rasterizationSamples, 1);
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const struct vk_multisample_state *ms = state->ms;
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pipeline->state.ms.rast_samples =
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create_info->pMultisampleState->rasterizationSamples;
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pipeline->state.ms.sample_mask =
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create_info->pMultisampleState->pSampleMask
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? create_info->pMultisampleState->pSampleMask[0]
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: UINT16_MAX;
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if (!ms)
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return;
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unsigned nr_samples = MAX2(ms->rasterization_samples, 1);
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pipeline->state.ms.rast_samples = ms->rasterization_samples;
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pipeline->state.ms.sample_mask = ms->sample_mask;
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pipeline->state.ms.min_samples =
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MAX2(create_info->pMultisampleState->minSampleShading * nr_samples, 1);
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MAX2(ms->min_sample_shading * nr_samples, 1);
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}
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static enum mali_stencil_op
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@ -656,18 +645,14 @@ translate_compare_func(VkCompareOp comp)
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static void
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parse_zs(struct panvk_graphics_pipeline *pipeline,
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const VkGraphicsPipelineCreateInfo *create_info)
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const struct vk_graphics_pipeline_state *state)
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{
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VK_FROM_HANDLE(vk_render_pass, pass, create_info->renderPass);
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const struct vk_subpass *subpass = &pass->subpasses[create_info->subpass];
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bool use_depth_stencil_attachment =
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subpass->depth_stencil_attachment &&
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subpass->depth_stencil_attachment->attachment != VK_ATTACHMENT_UNUSED;
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const struct vk_depth_stencil_state *ds = state->ds;
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if (!use_depth_stencil_attachment)
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if (!ds)
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return;
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pipeline->state.zs.z_test = create_info->pDepthStencilState->depthTestEnable;
|
||||
pipeline->state.zs.z_test = ds->depth.test_enable;
|
||||
|
||||
/* The Vulkan spec says:
|
||||
*
|
||||
|
|
@ -679,68 +664,53 @@ parse_zs(struct panvk_graphics_pipeline *pipeline,
|
|||
* condition ourselves.
|
||||
*/
|
||||
pipeline->state.zs.z_write =
|
||||
pipeline->state.zs.z_test &&
|
||||
create_info->pDepthStencilState->depthWriteEnable;
|
||||
pipeline->state.zs.z_test && ds->depth.write_enable;
|
||||
|
||||
pipeline->state.zs.z_compare_func =
|
||||
translate_compare_func(create_info->pDepthStencilState->depthCompareOp);
|
||||
pipeline->state.zs.s_test =
|
||||
create_info->pDepthStencilState->stencilTestEnable;
|
||||
translate_compare_func(ds->depth.compare_op);
|
||||
pipeline->state.zs.s_test = ds->stencil.test_enable;
|
||||
pipeline->state.zs.s_front.fail_op =
|
||||
translate_stencil_op(create_info->pDepthStencilState->front.failOp);
|
||||
translate_stencil_op(ds->stencil.front.op.fail);
|
||||
pipeline->state.zs.s_front.pass_op =
|
||||
translate_stencil_op(create_info->pDepthStencilState->front.passOp);
|
||||
translate_stencil_op(ds->stencil.front.op.pass);
|
||||
pipeline->state.zs.s_front.z_fail_op =
|
||||
translate_stencil_op(create_info->pDepthStencilState->front.depthFailOp);
|
||||
translate_stencil_op(ds->stencil.front.op.depth_fail);
|
||||
pipeline->state.zs.s_front.compare_func =
|
||||
translate_compare_func(create_info->pDepthStencilState->front.compareOp);
|
||||
pipeline->state.zs.s_front.compare_mask =
|
||||
create_info->pDepthStencilState->front.compareMask;
|
||||
pipeline->state.zs.s_front.write_mask =
|
||||
create_info->pDepthStencilState->front.writeMask;
|
||||
pipeline->state.zs.s_front.ref =
|
||||
create_info->pDepthStencilState->front.reference;
|
||||
translate_compare_func(ds->stencil.front.op.compare);
|
||||
pipeline->state.zs.s_front.compare_mask = ds->stencil.front.compare_mask;
|
||||
pipeline->state.zs.s_front.write_mask = ds->stencil.front.write_mask;
|
||||
pipeline->state.zs.s_front.ref = ds->stencil.front.reference;
|
||||
pipeline->state.zs.s_back.fail_op =
|
||||
translate_stencil_op(create_info->pDepthStencilState->back.failOp);
|
||||
translate_stencil_op(ds->stencil.back.op.fail);
|
||||
pipeline->state.zs.s_back.pass_op =
|
||||
translate_stencil_op(create_info->pDepthStencilState->back.passOp);
|
||||
translate_stencil_op(ds->stencil.back.op.pass);
|
||||
pipeline->state.zs.s_back.z_fail_op =
|
||||
translate_stencil_op(create_info->pDepthStencilState->back.depthFailOp);
|
||||
translate_stencil_op(ds->stencil.back.op.depth_fail);
|
||||
pipeline->state.zs.s_back.compare_func =
|
||||
translate_compare_func(create_info->pDepthStencilState->back.compareOp);
|
||||
pipeline->state.zs.s_back.compare_mask =
|
||||
create_info->pDepthStencilState->back.compareMask;
|
||||
pipeline->state.zs.s_back.write_mask =
|
||||
create_info->pDepthStencilState->back.writeMask;
|
||||
pipeline->state.zs.s_back.ref =
|
||||
create_info->pDepthStencilState->back.reference;
|
||||
translate_compare_func(ds->stencil.back.op.compare);
|
||||
pipeline->state.zs.s_back.compare_mask = ds->stencil.back.compare_mask;
|
||||
pipeline->state.zs.s_back.write_mask = ds->stencil.back.write_mask;
|
||||
pipeline->state.zs.s_back.ref = ds->stencil.back.reference;
|
||||
}
|
||||
|
||||
static void
|
||||
parse_rast(struct panvk_graphics_pipeline *pipeline,
|
||||
const VkGraphicsPipelineCreateInfo *create_info)
|
||||
const struct vk_graphics_pipeline_state *state)
|
||||
{
|
||||
pipeline->state.rast.clamp_depth =
|
||||
create_info->pRasterizationState->depthClampEnable;
|
||||
pipeline->state.rast.depth_bias.enable =
|
||||
create_info->pRasterizationState->depthBiasEnable;
|
||||
pipeline->state.rast.depth_bias.constant_factor =
|
||||
create_info->pRasterizationState->depthBiasConstantFactor;
|
||||
pipeline->state.rast.depth_bias.clamp =
|
||||
create_info->pRasterizationState->depthBiasClamp;
|
||||
pipeline->state.rast.depth_bias.slope_factor =
|
||||
create_info->pRasterizationState->depthBiasSlopeFactor;
|
||||
const struct vk_rasterization_state *rs = state->rs;
|
||||
|
||||
pipeline->state.rast.clamp_depth = rs->depth_clamp_enable;
|
||||
pipeline->state.rast.depth_bias.enable = rs->depth_bias.enable;
|
||||
pipeline->state.rast.depth_bias.constant_factor = rs->depth_bias.constant;
|
||||
pipeline->state.rast.depth_bias.clamp = rs->depth_bias.clamp;
|
||||
pipeline->state.rast.depth_bias.slope_factor = rs->depth_bias.slope;
|
||||
pipeline->state.rast.front_ccw =
|
||||
create_info->pRasterizationState->frontFace ==
|
||||
VK_FRONT_FACE_COUNTER_CLOCKWISE;
|
||||
rs->front_face == VK_FRONT_FACE_COUNTER_CLOCKWISE;
|
||||
pipeline->state.rast.cull_front_face =
|
||||
create_info->pRasterizationState->cullMode & VK_CULL_MODE_FRONT_BIT;
|
||||
pipeline->state.rast.cull_back_face =
|
||||
create_info->pRasterizationState->cullMode & VK_CULL_MODE_BACK_BIT;
|
||||
pipeline->state.rast.line_width =
|
||||
create_info->pRasterizationState->lineWidth;
|
||||
pipeline->state.rast.enable =
|
||||
!create_info->pRasterizationState->rasterizerDiscardEnable;
|
||||
rs->cull_mode & VK_CULL_MODE_FRONT_BIT;
|
||||
pipeline->state.rast.cull_back_face = rs->cull_mode & VK_CULL_MODE_BACK_BIT;
|
||||
pipeline->state.rast.line_width = rs->line.width;
|
||||
pipeline->state.rast.enable = !rs->rasterizer_discard_enable;
|
||||
}
|
||||
|
||||
static bool
|
||||
|
|
@ -764,26 +734,22 @@ fs_required(struct panvk_graphics_pipeline *pipeline)
|
|||
return (info->fs.writes_depth || info->fs.writes_stencil);
|
||||
}
|
||||
|
||||
#define PANVK_DYNAMIC_FS_RSD_MASK \
|
||||
((1 << VK_DYNAMIC_STATE_DEPTH_BIAS) | \
|
||||
(1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS) | \
|
||||
(1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK) | \
|
||||
(1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK) | \
|
||||
(1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
|
||||
|
||||
static void
|
||||
init_fs_state(struct panvk_graphics_pipeline *pipeline,
|
||||
const VkGraphicsPipelineCreateInfo *create_info,
|
||||
const struct vk_graphics_pipeline_state *state,
|
||||
struct panvk_shader *shader)
|
||||
{
|
||||
if (!shader)
|
||||
return;
|
||||
|
||||
pipeline->state.fs.dynamic_rsd =
|
||||
pipeline->state.dynamic_mask & PANVK_DYNAMIC_FS_RSD_MASK;
|
||||
pipeline->state.fs.dynamic_rsd = is_dyn(state, RS_DEPTH_BIAS_FACTORS) ||
|
||||
is_dyn(state, CB_BLEND_CONSTANTS) ||
|
||||
is_dyn(state, DS_STENCIL_COMPARE_MASK) ||
|
||||
is_dyn(state, DS_STENCIL_WRITE_MASK) ||
|
||||
is_dyn(state, DS_STENCIL_REFERENCE);
|
||||
pipeline->state.fs.address = upload_shader(&pipeline->base, shader);
|
||||
pipeline->state.fs.info = shader->info;
|
||||
pipeline->state.fs.rt_mask = get_active_color_attachments(create_info, NULL);
|
||||
pipeline->state.fs.rt_mask = get_active_color_attachments(state);
|
||||
pipeline->state.fs.required = fs_required(pipeline);
|
||||
}
|
||||
|
||||
|
|
@ -867,43 +833,32 @@ collect_varyings(struct panvk_graphics_pipeline *pipeline,
|
|||
|
||||
static void
|
||||
parse_vertex_input(struct panvk_graphics_pipeline *pipeline,
|
||||
const VkGraphicsPipelineCreateInfo *create_info,
|
||||
const struct vk_graphics_pipeline_state *state,
|
||||
struct panvk_shader **shaders)
|
||||
{
|
||||
struct panvk_attribs_info *attribs = &pipeline->state.vs.attribs;
|
||||
const VkPipelineVertexInputStateCreateInfo *info =
|
||||
create_info->pVertexInputState;
|
||||
const struct vk_vertex_input_state *vi = state->vi;
|
||||
|
||||
const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_info =
|
||||
vk_find_struct_const(info->pNext,
|
||||
PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
|
||||
attribs->buf_count = util_last_bit(vi->bindings_valid);
|
||||
for (unsigned i = 0; i < attribs->buf_count; i++) {
|
||||
if (!(vi->bindings_valid & BITFIELD_BIT(i)))
|
||||
continue;
|
||||
|
||||
for (unsigned i = 0; i < info->vertexBindingDescriptionCount; i++) {
|
||||
const VkVertexInputBindingDescription *desc =
|
||||
&info->pVertexBindingDescriptions[i];
|
||||
attribs->buf_count = MAX2(desc->binding + 1, attribs->buf_count);
|
||||
attribs->buf[desc->binding].stride = desc->stride;
|
||||
attribs->buf[desc->binding].per_instance =
|
||||
desc->inputRate == VK_VERTEX_INPUT_RATE_INSTANCE;
|
||||
attribs->buf[desc->binding].instance_divisor = 1;
|
||||
}
|
||||
const struct vk_vertex_binding_state *desc = &vi->bindings[i];
|
||||
|
||||
if (div_info) {
|
||||
for (unsigned i = 0; i < div_info->vertexBindingDivisorCount; i++) {
|
||||
const VkVertexInputBindingDivisorDescriptionEXT *div =
|
||||
&div_info->pVertexBindingDivisors[i];
|
||||
attribs->buf[div->binding].instance_divisor = div->divisor;
|
||||
}
|
||||
attribs->buf[i].stride = desc->stride;
|
||||
attribs->buf[i].per_instance =
|
||||
desc->input_rate == VK_VERTEX_INPUT_RATE_INSTANCE;
|
||||
attribs->buf[i].instance_divisor = desc->divisor;
|
||||
}
|
||||
|
||||
const struct pan_shader_info *vs = &shaders[MESA_SHADER_VERTEX]->info;
|
||||
uint32_t vi_attrib_count = util_last_bit(vi->attributes_valid);
|
||||
|
||||
attribs->attrib_count = 0;
|
||||
for (unsigned i = 0; i < info->vertexAttributeDescriptionCount; i++) {
|
||||
const VkVertexInputAttributeDescription *desc =
|
||||
&info->pVertexAttributeDescriptions[i];
|
||||
|
||||
unsigned attrib = desc->location + VERT_ATTRIB_GENERIC0;
|
||||
for (unsigned i = 0; i < vi_attrib_count; i++) {
|
||||
const struct vk_vertex_attribute_state *desc = &vi->attributes[i];
|
||||
unsigned attrib = i + VERT_ATTRIB_GENERIC0;
|
||||
unsigned slot =
|
||||
util_bitcount64(vs->attributes_read & BITFIELD64_MASK(attrib));
|
||||
|
||||
|
|
@ -922,6 +877,15 @@ panvk_graphics_pipeline_create(struct panvk_device *dev,
|
|||
struct panvk_pipeline **out)
|
||||
{
|
||||
VK_FROM_HANDLE(panvk_pipeline_layout, layout, create_info->layout);
|
||||
struct vk_graphics_pipeline_all_state all;
|
||||
struct vk_graphics_pipeline_state state = {};
|
||||
VkResult result;
|
||||
|
||||
result = vk_graphics_pipeline_state_fill(&dev->vk, &state, create_info, NULL,
|
||||
0, &all, NULL, 0, NULL);
|
||||
if (result)
|
||||
return result;
|
||||
|
||||
struct panvk_graphics_pipeline *gfx_pipeline = vk_object_zalloc(
|
||||
&dev->vk, alloc, sizeof(*gfx_pipeline), VK_OBJECT_TYPE_PIPELINE);
|
||||
|
||||
|
|
@ -931,6 +895,10 @@ panvk_graphics_pipeline_create(struct panvk_device *dev,
|
|||
*out = &gfx_pipeline->base;
|
||||
gfx_pipeline->base.layout = layout;
|
||||
gfx_pipeline->base.type = PANVK_PIPELINE_GRAPHICS;
|
||||
gfx_pipeline->state.dynamic.vi = &gfx_pipeline->state.vi;
|
||||
gfx_pipeline->state.dynamic.ms.sample_locations = &gfx_pipeline->state.sl;
|
||||
vk_dynamic_graphics_state_fill(&gfx_pipeline->state.dynamic, &state);
|
||||
gfx_pipeline->state.rp = *state.rp;
|
||||
|
||||
panvk_pool_init(&gfx_pipeline->base.bin_pool, dev, NULL,
|
||||
PAN_KMOD_BO_FLAG_EXECUTABLE, 4096,
|
||||
|
|
@ -940,19 +908,19 @@ panvk_graphics_pipeline_create(struct panvk_device *dev,
|
|||
|
||||
struct panvk_shader *shaders[MESA_SHADER_STAGES] = {NULL};
|
||||
|
||||
parse_dynamic_state(gfx_pipeline, create_info);
|
||||
parse_color_blend(gfx_pipeline, create_info);
|
||||
parse_dynamic_state(gfx_pipeline, &state);
|
||||
parse_color_blend(gfx_pipeline, &state);
|
||||
compile_shaders(&gfx_pipeline->base, create_info->pStages,
|
||||
create_info->stageCount, alloc, shaders);
|
||||
collect_varyings(gfx_pipeline, shaders);
|
||||
parse_input_assembly(gfx_pipeline, create_info);
|
||||
parse_multisample(gfx_pipeline, create_info);
|
||||
parse_zs(gfx_pipeline, create_info);
|
||||
parse_rast(gfx_pipeline, create_info);
|
||||
parse_vertex_input(gfx_pipeline, create_info, shaders);
|
||||
init_fs_state(gfx_pipeline, create_info, shaders[MESA_SHADER_FRAGMENT]);
|
||||
parse_input_assembly(gfx_pipeline, &state);
|
||||
parse_multisample(gfx_pipeline, &state);
|
||||
parse_zs(gfx_pipeline, &state);
|
||||
parse_rast(gfx_pipeline, &state);
|
||||
parse_vertex_input(gfx_pipeline, &state, shaders);
|
||||
init_fs_state(gfx_pipeline, &state, shaders[MESA_SHADER_FRAGMENT]);
|
||||
init_shaders(&gfx_pipeline->base, create_info, shaders);
|
||||
parse_viewport(gfx_pipeline, create_info);
|
||||
parse_viewport(gfx_pipeline, &state);
|
||||
|
||||
release_shaders(&gfx_pipeline->base, shaders, alloc);
|
||||
return VK_SUCCESS;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue