r300g: add "has HiZ" flag, add ZMask regs

This commit is contained in:
Marek Olšák 2010-06-24 03:02:50 +02:00
parent 7315300fa5
commit 6b15a8d2af
3 changed files with 23 additions and 0 deletions

View file

@ -36,6 +36,7 @@ void r300_parse_chipset(struct r300_capabilities* caps)
caps->num_vert_fpus = 2;
caps->num_tex_units = 16;
caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;
caps->has_hiz = TRUE;
caps->is_r400 = FALSE;
caps->is_r500 = FALSE;
caps->high_second_pipe = FALSE;
@ -76,6 +77,7 @@ void r300_parse_chipset(struct r300_capabilities* caps)
case 0x4E54:
case 0x4E56:
caps->family = CHIP_FAMILY_RV350;
caps->has_hiz = FALSE;
caps->high_second_pipe = TRUE;
break;
@ -106,6 +108,7 @@ void r300_parse_chipset(struct r300_capabilities* caps)
case 0x5B64:
case 0x5B65:
caps->family = CHIP_FAMILY_RV370;
caps->has_hiz = FALSE;
caps->high_second_pipe = TRUE;
break;

View file

@ -42,6 +42,8 @@ struct r300_capabilities {
unsigned num_tex_units;
/* Whether or not TCL is physically present */
boolean has_tcl;
/* Some chipsets do not have HiZ RAM. */
boolean has_hiz;
/* Whether or not this is RV350 or newer, including all r400 and r500
* chipsets. The differences compared to the oldest r300 chips are:
* - Blend LTE/GTE thresholds

View file

@ -2673,6 +2673,24 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Z Buffer Clear Value */
#define R300_ZB_DEPTHCLEARVALUE 0x4f28
/* Z Mask RAM is a Z compression buffer.
* Each dword of the Z Mask contains compression info for 16 4x4 pixel blocks,
* that is 2 bits for each block.
* On chips with 2 Z pipes, every other dword maps to a different pipe.
*/
/* The dword offset into Z mask RAM (bits 18:4) */
#define R300_ZB_ZMASK_OFFSET 0x4f30
/* Z Mask Pitch. */
#define R300_ZB_ZMASK_PITCH 0x4f34
/* Access to Z Mask RAM in a manner similar to HiZ RAM.
* The indices are autoincrementing. */
#define R300_ZB_ZMASK_WRINDEX 0x4f38
#define R300_ZB_ZMASK_DWORD 0x4f3c
#define R300_ZB_ZMASK_RDINDEX 0x4f40
/* Hierarchical Z Memory Offset */
#define R300_ZB_HIZ_OFFSET 0x4f44