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intel: Enable more LOD0 HIZ+CCS fast clears

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For correct fast-clearing with HiZ+CCS, we require roughly 16x8
alignment of LODs. The next patch will cause drivers to ignore the
alignment of LOD0, so align the qpitch to 8 to avoid breakage and so
that fast clears will be enabled more often.

Prevents failures with the piglit test case:

	./bin/fbo-depth-array depth-clear -fbo

in the next patch.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30250>
This commit is contained in:
Nanley Chery 2024-07-08 20:24:40 -04:00 • committed by Marge Bot
parent d22d6d814d
commit 6afdc9c5a6
2 changed files with 16 additions and 4 deletions
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5
src/intel/blorp/blorp_clear.c
View file

@ -981,11 +981,8 @@ blorp_can_hiz_clear_depth(const struct intel_device_info *devinfo,
(max_x1_y1 ? haligned_x1 % 16 || valigned_y1 % 8 :
x1 % 16 || y1 % 8);
const bool partial_clear = x0 > 0 || y0 > 0 || !max_x1_y1;
const bool multislice_surf = surf->levels > 1 ||
surf->logical_level0_px.depth > 1 ||
surf->logical_level0_px.array_len > 1;
if (unaligned && (partial_clear || multislice_surf))
if (unaligned && (partial_clear || surf->levels > 1))
return false;
}

15
src/intel/isl/isl.c
View file

@ -1862,6 +1862,21 @@ isl_calc_array_pitch_el_rows_gfx4_2d(
pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
}
if (isl_surf_usage_is_depth(info->usage) &&
_isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
/* From the TGL PRM, Vol 9, "Compressed Depth Buffers" (under the
* "Texture performant" and "ZCS" columns):
*
* Update with clear at either 16x8 or 8x4 granularity, based on
* fs_clr or otherwise.
*
* When fast-clearing, hardware behaves in unexpected ways if the clear
* rectangle, aligned to 16x8, could cover neighboring LODs. Align the
* array pitch to 8 in order to increase the number of aligned LODs.
*/
pitch_el_rows = isl_align(pitch_el_rows, 8);
}
return pitch_el_rows;
}