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panfrost/midgard: Fix swizzle for store instructions

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The current logic considers that the nir_intrinsic_component(store_intr)
encodes the source components start, but it actually encodes the
destination one. Source component offset adjustment is taken care of in
install_registers_instr(), when offset_swizzle() is called.

This fixes dEQP-GLES2.functional.shaders.random.all_features.fragment.45
when PAN_MESA_DEBUG=deqp (looks like exposing GLES3 features has an
impact on the varyings layout).

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3429>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3429>
This commit is contained in:
Boris Brezillon 2020-01-16 11:20:06 +01:00 • committed by Marge Bot
parent be95c816a7
commit 6af63c939b
1 changed files with 15 additions and 3 deletions
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18
src/panfrost/midgard/midgard_compile.c
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@ -1554,7 +1554,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
emit_explicit_constant(ctx, reg, reg);
unsigned component = nir_intrinsic_component(instr);
unsigned dst_component = nir_intrinsic_component(instr);
unsigned nr_comp = nir_src_num_components(instr->src[0]);
midgard_instruction st = m_st_vary_32(reg, offset);
@ -1577,8 +1577,20 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
break;
}
for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle[0]); ++i)
st.swizzle[0][i] = MIN2(i + component, nr_comp);
/* nir_intrinsic_component(store_intr) encodes the
* destination component start. Source component offset
* adjustment is taken care of in
* install_registers_instr(), when offset_swizzle() is
* called.
*/
unsigned src_component = COMPONENT_X;
assert(nr_comp > 0);
for (unsigned i = 0; i < ARRAY_SIZE(st.swizzle); ++i) {
st.swizzle[0][i] = src_component;
if (i >= dst_component && i < dst_component + nr_comp - 1)
src_component++;
}
emit_mir_instruction(ctx, st);
} else {