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i965/wm: Surface state overrides for configuring w-tiled as y-tiled

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v2: Use intel_mipmap_tree::total_width in order to get correct alignment
    automatically. Also use "mt->total_height / mt->physical_depth0" as
    surface height allowing hardware to offset to correct slice.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Topi Pohjolainen 2014-05-07 10:49:50 +03:00
parent 103057b2b7
commit 6aefaa4eb2
2 changed files with 30 additions and 0 deletions
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6
src/mesa/drivers/dri/i965/brw_state.h
View file

@ -206,6 +206,12 @@ void gen4_init_vtable_surface_functions(struct brw_context *brw);
uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
void brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
bool is_render_target,
unsigned *width, unsigned *height,
unsigned *pitch, uint32_t *tiling,
unsigned *format);
uint32_t brw_format_for_mesa_format(mesa_format mesa_format);
GLuint translate_tex_target(GLenum target);

24
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View file

@ -101,6 +101,30 @@ brw_get_surface_num_multisamples(unsigned num_samples)
return BRW_SURFACE_MULTISAMPLECOUNT_1;
}
void
brw_configure_w_tiled(const struct intel_mipmap_tree *mt,
bool is_render_target,
unsigned *width, unsigned *height,
unsigned *pitch, uint32_t *tiling, unsigned *format)
{
static const unsigned halign_stencil = 8;
/* In Y-tiling row is twice as wide as in W-tiling, and subsequently
* there are half as many rows.
* In addition, mip-levels are accessed manually by the program and
* therefore the surface is setup to cover all the mip-levels for one slice.
* (Hardware is still used to access individual slices).
*/
*tiling = I915_TILING_Y;
*pitch = mt->pitch * 2;
*width = ALIGN(mt->total_width, halign_stencil) * 2;
*height = (mt->total_height / mt->physical_depth0) / 2;
if (is_render_target) {
*format = BRW_SURFACEFORMAT_R8_UINT;
}
}
/**
* Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle