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radeonsi/gfx9: fix and enable single-sample CMASK fast clear

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-03-28 03:34:06 +02:00
parent d4bb4583b0
commit 6ab2042761
2 changed files with 11 additions and 4 deletions
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8
src/gallium/drivers/radeon/r600_texture.c
View file

@ -2639,10 +2639,6 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
if (rctx->render_cond)
return;
/* TODO: fix CMASK and DCC fast clear */
if (rctx->chip_class >= GFX9)
return;
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
@ -2710,6 +2706,10 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
uint32_t reset_value;
bool clear_words_needed;
/* TODO: fix DCC clear */
if (rctx->chip_class >= GFX9)
continue;
if (rctx->screen->debug_flags & DBG_NO_DCC_CLEAR)
continue;

7
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -655,6 +655,13 @@ static int gfx9_compute_miptree(struct amdgpu_winsys *ws,
surf->u.gfx9.surf.swizzle_mode = in->swizzleMode;
surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 :
out.mipChainPitch - 1;
/* CMASK fast clear uses these even if FMASK isn't allocated.
* FMASK only supports the Z swizzle modes, whose numbers are multiples of 4.
*/
surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3;
surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch;
surf->u.gfx9.surf_slice_size = out.sliceSize;
surf->u.gfx9.surf_pitch = out.pitch;
surf->u.gfx9.surf_height = out.height;