From 69fc7ee6220072b013bd0fae4338db1474c4e1f5 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Mon, 22 Apr 2024 21:01:11 -0700 Subject: [PATCH] intel/disasm: Fix cache load/store disassembly for URB messages Signed-off-by: Sagar Ghuge Reviewed-by: Caio Oliveira Part-of: --- src/intel/compiler/brw_disasm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 6cab08cfc97..64580ef6dda 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -2254,6 +2254,8 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, case LSC_OP_LOAD: format(file, ","); err |= control(file, "cache_load", + devinfo->ver >= 20 ? + xe2_lsc_cache_load : lsc_cache_load, lsc_msg_desc_cache_ctrl(devinfo, imm_desc), &space); @@ -2261,6 +2263,8 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, default: format(file, ","); err |= control(file, "cache_store", + devinfo->ver >= 20 ? + xe2_lsc_cache_store : lsc_cache_store, lsc_msg_desc_cache_ctrl(devinfo, imm_desc), &space);