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nir: Collapse more SSA checks
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24432>
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312089fea7
commit
696fdde485
13 changed files with 20 additions and 66 deletions
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@ -347,7 +347,7 @@ nir_vec_scalars(nir_builder *build, nir_ssa_scalar *comp, unsigned num_component
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nir_ssa_def *
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nir_ssa_for_src(nir_builder *build, nir_src src, int num_components)
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{
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if (src.is_ssa && src.ssa->num_components == num_components)
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if (src.ssa->num_components == num_components)
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return src.ssa;
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assert((unsigned)num_components <= nir_src_num_components(src));
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@ -498,7 +498,7 @@ nir_vec_scalars(nir_builder *build, nir_ssa_scalar *comp, unsigned num_component
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static inline nir_ssa_def *
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nir_mov_alu(nir_builder *build, nir_alu_src src, unsigned num_components)
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{
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if (src.src.is_ssa && src.src.ssa->num_components == num_components) {
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if (src.src.ssa->num_components == num_components) {
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bool any_swizzles = false;
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for (unsigned i = 0; i < num_components; i++) {
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if (src.swizzle[i] != i)
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@ -567,13 +567,8 @@ update_if_uses(nir_cf_node *node)
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nir_if *if_stmt = nir_cf_node_as_if(node);
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nir_src_set_parent_if(&if_stmt->condition, if_stmt);
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if (if_stmt->condition.is_ssa) {
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list_addtail(&if_stmt->condition.use_link,
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&if_stmt->condition.ssa->uses);
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} else {
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list_addtail(&if_stmt->condition.use_link,
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&if_stmt->condition.reg.reg->uses);
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}
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list_addtail(&if_stmt->condition.use_link,
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&if_stmt->condition.ssa->uses);
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}
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/**
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@ -77,10 +77,8 @@ copy_types(nir_src src, nir_dest *dest, BITSET_WORD *float_types,
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BITSET_WORD *int_types, bool *progress)
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{
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bool src_is_sink = nir_src_is_const(src) || nir_src_is_undef(src);
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if (src.is_ssa && dest->is_ssa) {
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copy_type(src.ssa->index, dest->ssa.index, src_is_sink, float_types, progress);
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copy_type(src.ssa->index, dest->ssa.index, src_is_sink, int_types, progress);
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}
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copy_type(src.ssa->index, dest->ssa.index, src_is_sink, float_types, progress);
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copy_type(src.ssa->index, dest->ssa.index, src_is_sink, int_types, progress);
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}
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/** Gather up ALU types for SSA values
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@ -258,7 +258,7 @@ nir_get_live_ssa_defs(nir_cursor cursor, void *mem_ctx)
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static bool
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src_does_not_use_def(nir_src *src, void *def)
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{
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return !src->is_ssa || src->ssa != (nir_ssa_def *)def;
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return src->ssa != (nir_ssa_def *)def;
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}
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static bool
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@ -277,8 +277,7 @@ search_for_use_after_instr(nir_instr *start, nir_ssa_def *def)
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* so we need to also check the following if condition, if any.
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*/
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nir_if *following_if = nir_block_get_following_if(start->block);
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if (following_if && following_if->condition.is_ssa &&
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following_if->condition.ssa == def)
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if (following_if && following_if->condition.ssa == def)
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return true;
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return false;
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@ -30,13 +30,13 @@
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static bool
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is_dest_live(const nir_dest *dest, BITSET_WORD *defs_live)
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{
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return !dest->is_ssa || BITSET_TEST(defs_live, dest->ssa.index);
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return BITSET_TEST(defs_live, dest->ssa.index);
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}
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static bool
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mark_src_live(const nir_src *src, BITSET_WORD *defs_live)
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{
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if (src->is_ssa && !BITSET_TEST(defs_live, src->ssa->index)) {
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if (!BITSET_TEST(defs_live, src->ssa->index)) {
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BITSET_SET(defs_live, src->ssa->index);
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return true;
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} else {
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@ -1467,11 +1467,11 @@ opt_if_merge(nir_if *nif)
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bool progress = false;
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nir_block *next_blk = nir_cf_node_cf_tree_next(&nif->cf_node);
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if (!next_blk || !nif->condition.is_ssa)
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if (!next_blk)
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return false;
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nir_if *next_if = nir_block_get_following_if(next_blk);
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if (!next_if || !next_if->condition.is_ssa)
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if (!next_if)
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return false;
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/* Here we merge two consecutive ifs that have the same condition e.g:
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@ -51,18 +51,6 @@
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* lower register pressure.
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*/
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static inline bool
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src_is_ssa(nir_src *src, void *state)
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{
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return src->is_ssa;
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}
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static inline bool
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instr_reads_register(nir_instr *instr)
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{
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return !nir_foreach_src(instr, src_is_ssa, NULL);
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}
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static bool
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nir_opt_move_block(nir_block *block, nir_move_options options)
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{
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@ -80,16 +68,9 @@ nir_opt_move_block(nir_block *block, nir_move_options options)
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* the original order is kept.
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*/
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unsigned index = 1;
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unsigned last_reg_def_index = 0;
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nir_foreach_instr_reverse_safe(instr, block) {
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instr->index = index++;
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/* Don't move register defs */
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if (nir_instr_def_is_register(instr)) {
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last_reg_def_index = instr->index;
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continue;
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}
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/* Check if this instruction can be moved downwards */
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if (!nir_can_move_instr(instr, options))
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continue;
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@ -114,12 +95,6 @@ nir_opt_move_block(nir_block *block, nir_move_options options)
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if (nir_instr_prev(first_user) == instr)
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continue;
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/* Don't move register reads past register defs */
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if (first_user->index < last_reg_def_index &&
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instr_reads_register(instr)) {
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continue;
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}
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/* Insert the instruction before it's first user */
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exec_node_remove(&instr->node);
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instr->index = first_user->index;
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@ -43,9 +43,7 @@ try_extract_const_addition(nir_builder *b, nir_ssa_scalar val, opt_offsets_state
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return val;
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nir_alu_instr *alu = nir_instr_as_alu(val.def->parent_instr);
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if (alu->op != nir_op_iadd ||
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!alu->src[0].src.is_ssa ||
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!alu->src[1].src.is_ssa)
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if (alu->op != nir_op_iadd)
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return val;
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nir_ssa_scalar src[2] = {
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@ -115,7 +113,7 @@ try_fold_load_store(nir_builder *b,
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nir_src *off_src = &intrin->src[offset_src_idx];
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nir_ssa_def *replace_src = NULL;
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if (!off_src->is_ssa || off_src->ssa->bit_size != 32)
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if (off_src->ssa->bit_size != 32)
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return false;
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if (!nir_src_is_const(*off_src)) {
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@ -82,7 +82,7 @@ opt_shrink_store_instr(nir_builder *b, nir_intrinsic_instr *instr, bool shrink_i
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/* Trim the num_components stored according to the write mask. */
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unsigned write_mask = nir_intrinsic_write_mask(instr);
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unsigned last_bit = util_last_bit(write_mask);
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if (last_bit < instr->num_components && instr->src[0].is_ssa) {
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if (last_bit < instr->num_components) {
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nir_ssa_def *def = nir_trim_vector(b, instr->src[0].ssa, last_bit);
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nir_instr_rewrite_src(&instr->instr,
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&instr->src[0],
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@ -76,8 +76,7 @@ opt_undef_vecN(nir_builder *b, nir_alu_instr *alu)
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return false;
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for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
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if (!alu->src[i].src.is_ssa ||
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alu->src[i].src.ssa->parent_instr->type != nir_instr_type_ssa_undef)
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if (alu->src[i].src.ssa->parent_instr->type != nir_instr_type_ssa_undef)
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return false;
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}
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@ -105,8 +104,7 @@ nir_get_undef_mask(nir_ssa_def *def)
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if (nir_op_is_vec(alu->op)) {
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for (int i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
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if (alu->src[i].src.is_ssa &&
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alu->src[i].src.ssa->parent_instr->type ==
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if (alu->src[i].src.ssa->parent_instr->type ==
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nir_instr_type_ssa_undef) {
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undef |= BITSET_MASK(nir_ssa_alu_instr_src_components(alu, i)) << i;
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}
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@ -26,11 +26,7 @@
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static void
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add_src(nir_src *src, struct set *invariants)
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{
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if (src->is_ssa) {
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_mesa_set_add(invariants, src->ssa);
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} else {
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_mesa_set_add(invariants, src->reg.reg);
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}
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_mesa_set_add(invariants, src->ssa);
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}
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static bool
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@ -43,11 +39,7 @@ add_src_cb(nir_src *src, void *state)
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static bool
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dest_is_invariant(nir_dest *dest, struct set *invariants)
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{
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if (dest->is_ssa) {
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return _mesa_set_search(invariants, &dest->ssa);
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} else {
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return _mesa_set_search(invariants, dest->reg.reg);
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}
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return _mesa_set_search(invariants, &dest->ssa);
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}
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static void
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@ -911,8 +911,7 @@ write_deref(write_ctx *ctx, const nir_deref_instr *deref)
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if (deref->deref_type == nir_deref_type_array ||
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deref->deref_type == nir_deref_type_ptr_as_array) {
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header.deref.packed_src_ssa_16bit =
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deref->arr.index.is_ssa && are_object_ids_16bit(ctx);
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header.deref.packed_src_ssa_16bit = are_object_ids_16bit(ctx);
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header.deref.in_bounds = deref->arr.in_bounds;
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}
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