fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-18 06:50:24 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

r600g: move aux_context and r600_screen_clear_buffer to drivers/radeon

Browse source 
This will be used in the next commit.
This commit is contained in:
Marek Olšák 2013-09-22 21:45:23 +02:00
parent 0cb9de1dd0
commit 68f6dec32e
6 changed files with 74 additions and 66 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

30
src/gallium/drivers/r600/r600_blit.c
View file

@ -413,7 +413,7 @@ static boolean is_simple_msaa_resolve(const struct pipe_blit_info *info)
}
static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
unsigned offset, unsigned size, unsigned char value);
unsigned offset, unsigned size, unsigned value);
static void evergreen_set_clear_color(struct pipe_surface *cbuf,
const union pipe_color_union *color)
@ -627,21 +627,17 @@ void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsig
}
static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
unsigned offset, unsigned size, unsigned char value)
unsigned offset, unsigned size, unsigned value)
{
struct r600_context *rctx = (struct r600_context*)ctx;
uint32_t v = value;
if (rctx->screen->has_cp_dma &&
rctx->b.chip_class >= EVERGREEN &&
offset % 4 == 0 && size % 4 == 0) {
uint32_t clear_value = v | (v << 8) | (v << 16) | (v << 24);
evergreen_cp_dma_clear_buffer(rctx, dst, offset, size, clear_value);
evergreen_cp_dma_clear_buffer(rctx, dst, offset, size, value);
} else if (rctx->screen->has_streamout && offset % 4 == 0 && size % 4 == 0) {
union pipe_color_union clear_value;
clear_value.ui[0] = v | (v << 8) | (v << 16) | (v << 24);
clear_value.ui[0] = value;
r600_flag_resource_cache_flush(rctx, dst);
@ -653,21 +649,14 @@ static void r600_clear_buffer(struct pipe_context *ctx, struct pipe_resource *ds
/* Flush again in case the 3D engine has been prefetching the resource. */
r600_flag_resource_cache_flush(rctx, dst);
} else {
char *map = r600_buffer_mmap_sync_with_rings(rctx, r600_resource(dst),
PIPE_TRANSFER_WRITE);
memset(map + offset, value, size);
uint32_t *map = r600_buffer_mmap_sync_with_rings(rctx, r600_resource(dst),
PIPE_TRANSFER_WRITE);
size /= 4;
for (unsigned i = 0; i < size; i++)
*map++ = value;
}
}
void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst,
unsigned offset, unsigned size, unsigned char value)
{
pipe_mutex_lock(rscreen->aux_context_lock);
r600_clear_buffer(rscreen->aux_context, dst, offset, size, value);
rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
pipe_mutex_unlock(rscreen->aux_context_lock);
}
static bool util_format_is_subsampled_2x1_32bpp(enum pipe_format format)
{
const struct util_format_description *desc = util_format_description(format);
@ -965,4 +954,5 @@ void r600_init_blit_functions(struct r600_context *rctx)
rctx->b.b.resource_copy_region = r600_resource_copy_region;
rctx->b.b.blit = r600_blit;
rctx->b.b.flush_resource = r600_flush_resource;
rctx->b.clear_buffer = r600_clear_buffer;
}

65
src/gallium/drivers/r600/r600_pipe.c
View file

@ -950,8 +950,7 @@ static void r600_destroy_screen(struct pipe_screen* pscreen)
if (!radeon_winsys_unref(rscreen->b.ws))
return;
pipe_mutex_destroy(rscreen->aux_context_lock);
rscreen->aux_context->destroy(rscreen->aux_context);
r600_common_screen_cleanup(&rscreen->b);
if (rscreen->global_pool) {
compute_memory_pool_delete(rscreen->global_pool);
@ -1197,6 +1196,34 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
return NULL;
}
/* Set functions first. */
rscreen->b.b.context_create = r600_create_context;
rscreen->b.b.destroy = r600_destroy_screen;
rscreen->b.b.get_name = r600_get_name;
rscreen->b.b.get_vendor = r600_get_vendor;
rscreen->b.b.get_param = r600_get_param;
rscreen->b.b.get_shader_param = r600_get_shader_param;
rscreen->b.b.get_paramf = r600_get_paramf;
rscreen->b.b.get_compute_param = r600_get_compute_param;
rscreen->b.b.get_timestamp = r600_get_timestamp;
if (rscreen->b.chip_class >= EVERGREEN) {
rscreen->b.b.is_format_supported = evergreen_is_format_supported;
} else {
rscreen->b.b.is_format_supported = r600_is_format_supported;
}
rscreen->b.b.fence_reference = r600_fence_reference;
rscreen->b.b.fence_signalled = r600_fence_signalled;
rscreen->b.b.fence_finish = r600_fence_finish;
rscreen->b.b.get_driver_query_info = r600_get_driver_query_info;
if (rscreen->b.info.has_uvd) {
rscreen->b.b.get_video_param = ruvd_get_video_param;
rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
} else {
rscreen->b.b.get_video_param = r600_get_video_param;
rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
}
r600_init_screen_resource_functions(&rscreen->b.b);
r600_common_screen_init(&rscreen->b, ws);
rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
@ -1266,36 +1293,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
return NULL;
}
rscreen->b.b.destroy = r600_destroy_screen;
rscreen->b.b.get_name = r600_get_name;
rscreen->b.b.get_vendor = r600_get_vendor;
rscreen->b.b.get_param = r600_get_param;
rscreen->b.b.get_shader_param = r600_get_shader_param;
rscreen->b.b.get_paramf = r600_get_paramf;
rscreen->b.b.get_compute_param = r600_get_compute_param;
rscreen->b.b.get_timestamp = r600_get_timestamp;
if (rscreen->b.chip_class >= EVERGREEN) {
rscreen->b.b.is_format_supported = evergreen_is_format_supported;
} else {
rscreen->b.b.is_format_supported = r600_is_format_supported;
}
rscreen->b.b.context_create = r600_create_context;
rscreen->b.b.fence_reference = r600_fence_reference;
rscreen->b.b.fence_signalled = r600_fence_signalled;
rscreen->b.b.fence_finish = r600_fence_finish;
rscreen->b.b.get_driver_query_info = r600_get_driver_query_info;
if (rscreen->b.info.has_uvd) {
rscreen->b.b.get_video_param = ruvd_get_video_param;
rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
} else {
rscreen->b.b.get_video_param = r600_get_video_param;
rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
}
r600_init_screen_resource_functions(&rscreen->b.b);
util_format_s3tc_init();
rscreen->fences.bo = NULL;
@ -1319,10 +1316,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
}
}
/* Create the auxiliary context. */
pipe_mutex_init(rscreen->aux_context_lock);
rscreen->aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
#if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
struct pipe_resource templ = {};

7
src/gallium/drivers/r600/r600_pipe.h
View file

@ -241,11 +241,6 @@ struct r600_screen {
struct r600_resource *trace_bo;
uint32_t *trace_ptr;
unsigned cs_count;
/* Auxiliary context. Mainly used to initialize resources.
* It must be locked prior to using and flushed before unlocking. */
struct pipe_context *aux_context;
pipe_mutex aux_context_lock;
};
struct r600_pipe_sampler_view {
@ -627,8 +622,6 @@ void evergreen_update_db_shader_control(struct r600_context * rctx);
/* r600_blit.c */
void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx,
struct pipe_resource *src, const struct pipe_box *src_box);
void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst,
unsigned offset, unsigned size, unsigned char value);
void r600_init_blit_functions(struct r600_context *rctx);
void r600_blit_decompress_depth(struct pipe_context *ctx,
struct r600_texture *texture,

6
src/gallium/drivers/r600/r600_texture.c
View file

@ -514,7 +514,7 @@ r600_texture_create_object(struct pipe_screen *screen,
*/
R600_ERR("r600: failed to create bo for htile buffers\n");
} else {
r600_screen_clear_buffer(rscreen, &rtex->htile->b.b, 0, htile_size, 0);
r600_screen_clear_buffer(&rscreen->b, &rtex->htile->b.b, 0, htile_size, 0);
}
}
@ -537,8 +537,8 @@ r600_texture_create_object(struct pipe_screen *screen,
if (rtex->cmask.size) {
/* Initialize the cmask to 0xCC (= compressed state). */
r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
rtex->cmask.offset, rtex->cmask.size, 0xCC);
r600_screen_clear_buffer(&rscreen->b, &rtex->cmask_buffer->b.b,
rtex->cmask.offset, rtex->cmask.size, 0xCCCCCCCC);
}
if (rscreen->b.debug_flags & DBG_VM) {

21
src/gallium/drivers/radeon/r600_pipe_common.c
View file

@ -53,6 +53,16 @@ void r600_common_screen_init(struct r600_common_screen *rscreen,
rscreen->family = rscreen->info.family;
rscreen->chip_class = rscreen->info.chip_class;
rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
/* Create the auxiliary context. */
pipe_mutex_init(rscreen->aux_context_lock);
rscreen->aux_context = rscreen->b.context_create(&rscreen->b, NULL);
}
void r600_common_screen_cleanup(struct r600_common_screen *rscreen)
{
pipe_mutex_destroy(rscreen->aux_context_lock);
rscreen->aux_context->destroy(rscreen->aux_context);
}
bool r600_common_context_init(struct r600_common_context *rctx,
@ -130,3 +140,14 @@ bool r600_can_dump_shader(struct r600_common_screen *rscreen,
return false;
}
}
void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
unsigned offset, unsigned size, unsigned value)
{
struct r600_common_context *rctx = (struct r600_common_context*)rscreen->aux_context;
pipe_mutex_lock(rscreen->aux_context_lock);
rctx->clear_buffer(&rctx->b, dst, offset, size, value);
rscreen->aux_context->flush(rscreen->aux_context, NULL, 0);
pipe_mutex_unlock(rscreen->aux_context_lock);
}

11
src/gallium/drivers/radeon/r600_pipe_common.h
View file

@ -151,6 +151,11 @@ struct r600_common_screen {
enum chip_class chip_class;
struct radeon_info info;
unsigned debug_flags;
/* Auxiliary context. Mainly used to initialize resources.
* It must be locked prior to using and flushed before unlocking. */
struct pipe_context *aux_context;
pipe_mutex aux_context_lock;
};
/* This encapsulates a state or an operation which can emitted into the GPU
@ -228,17 +233,23 @@ struct r600_common_context {
struct pipe_resource *src,
unsigned src_level,
const struct pipe_box *src_box);
void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
unsigned offset, unsigned size, unsigned value);
};
/* r600_common_pipe.c */
void r600_common_screen_init(struct r600_common_screen *rscreen,
struct radeon_winsys *ws);
void r600_common_screen_cleanup(struct r600_common_screen *rscreen);
bool r600_common_context_init(struct r600_common_context *rctx,
struct r600_common_screen *rscreen);
void r600_common_context_cleanup(struct r600_common_context *rctx);
void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r);
bool r600_can_dump_shader(struct r600_common_screen *rscreen,
const struct tgsi_token *tokens);
void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
unsigned offset, unsigned size, unsigned value);
/* r600_streamout.c */
void r600_streamout_buffers_dirty(struct r600_common_context *rctx);