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radv: stop emitting RMW context registers for updating sample locations

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RMW context registers have been removed in RadeonSI a while ago
because they don't seem good for performance.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18234>
This commit is contained in:
Samuel Pitoiset 2022-08-24 17:41:42 +02:00 • committed by Marge Bot
parent 2f5891108a
commit 68e69d002f
2 changed files with 6 additions and 13 deletions
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8
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1031,7 +1031,9 @@ static void
radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_sample_locations_state *sample_location = &cmd_buffer->state.dynamic.sample_location;
struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
uint32_t num_samples = (uint32_t)sample_location->per_pixel;
unsigned pa_sc_aa_config = pipeline->ms.pa_sc_aa_config;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t sample_locs_pixel[4][2] = {0};
VkOffset2D sample_locs[4][8]; /* 8 is the max. sample count supported */
@ -1099,8 +1101,10 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)
}
/* Emit the maximum sample distance and the centroid priority. */
radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG,
S_028BE0_MAX_SAMPLE_DIST(max_sample_dist), ~C_028BE0_MAX_SAMPLE_DIST);
pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST;
pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist);
radeon_set_context_reg(cs, R_028BE0_PA_SC_AA_CONFIG, pa_sc_aa_config);
radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
radeon_emit(cs, centroid_priority);

11
src/amd/vulkan/radv_cs.h
View file

@ -83,17 +83,6 @@ radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx,
radeon_emit(cs, value);
}
static inline void
radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned mask)
{
assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
assert(cs->cdw + 4 <= cs->max_dw);
radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
radeon_emit(cs, mask);
radeon_emit(cs, value);
}
static inline void
radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
{