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intel/compiler/xe2: Set SIMD mode for sampler messages

Browse source 
Since SIMD8 no longer exists, the SIMD modes enums have different names
and different values.

v2 (Francisco Jerez): Rebase on 07b9bfacc7 ("intel/compiler: Move
logical-send lowering to a separate file").

v3: Update brw_disasm.c with SIMD descriptions.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27305>
This commit is contained in:
Ian Romanick 2022-07-22 17:26:30 -07:00 • committed by Marge Bot
parent 84de7a88d3
commit 68da9e4dff
3 changed files with 29 additions and 7 deletions
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9
src/intel/compiler/brw_disasm.c
View file

@ -656,6 +656,13 @@ static const char *const gfx5_sampler_simd_mode[7] = {
[GFX10_SAMPLER_SIMD_MODE_SIMD16H] = "SIMD16H",
};
static const char *const xe2_sampler_simd_mode[7] = {
[XE2_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16",
[XE2_SAMPLER_SIMD_MODE_SIMD32] = "SIMD32",
[XE2_SAMPLER_SIMD_MODE_SIMD16H] = "SIMD16H",
[XE2_SAMPLER_SIMD_MODE_SIMD32H] = "SIMD32H",
};
static const char *const sampler_target_format[4] = {
[0] = "F",
[2] = "UD",
@ -2315,7 +2322,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
err |= control(file, "sampler message", xe2_sampler_msg_type,
brw_sampler_desc_msg_type(devinfo, imm_desc),
&space);
err |= control(file, "sampler simd mode", gfx5_sampler_simd_mode,
err |= control(file, "sampler simd mode", xe2_sampler_simd_mode,
brw_sampler_desc_simd_mode(devinfo, imm_desc),
&space);
if (brw_sampler_desc_return_format(devinfo, imm_desc)) {

5
src/intel/compiler/brw_eu_defines.h
View file

@ -1503,6 +1503,11 @@ enum brw_message_target {
#define GFX10_SAMPLER_SIMD_MODE_SIMD8H 5
#define GFX10_SAMPLER_SIMD_MODE_SIMD16H 6
#define XE2_SAMPLER_SIMD_MODE_SIMD16 1
#define XE2_SAMPLER_SIMD_MODE_SIMD32 2
#define XE2_SAMPLER_SIMD_MODE_SIMD16H 5
#define XE2_SAMPLER_SIMD_MODE_SIMD32H 6
/* GFX9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
* behavior by setting bit 22 of dword 2 in the message header. */
#define GFX9_SAMPLER_SIMD_MODE_SIMD8D 0

22
src/intel/compiler/brw_lower_logical_sends.cpp
View file

@ -1319,13 +1319,23 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
header_size, REG_SIZE * reg_unit(devinfo));
unsigned mlen = load_payload_inst->size_written / REG_SIZE;
unsigned simd_mode = 0;
if (payload_type_bit_size == 16) {
assert(devinfo->ver >= 11);
simd_mode = inst->exec_size <= 8 ? GFX10_SAMPLER_SIMD_MODE_SIMD8H :
GFX10_SAMPLER_SIMD_MODE_SIMD16H;
if (devinfo->ver < 20) {
if (payload_type_bit_size == 16) {
assert(devinfo->ver >= 11);
simd_mode = inst->exec_size <= 8 ? GFX10_SAMPLER_SIMD_MODE_SIMD8H :
GFX10_SAMPLER_SIMD_MODE_SIMD16H;
} else {
simd_mode = inst->exec_size <= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8 :
BRW_SAMPLER_SIMD_MODE_SIMD16;
}
} else {
simd_mode = inst->exec_size <= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8 :
BRW_SAMPLER_SIMD_MODE_SIMD16;
if (payload_type_bit_size == 16) {
simd_mode = inst->exec_size <= 16 ? XE2_SAMPLER_SIMD_MODE_SIMD16H :
XE2_SAMPLER_SIMD_MODE_SIMD32H;
} else {
simd_mode = inst->exec_size <= 16 ? XE2_SAMPLER_SIMD_MODE_SIMD16 :
XE2_SAMPLER_SIMD_MODE_SIMD32;
}
}
/* Generate the SEND. */