fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-01-02 16:00:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

radv/amdgpu: Allow multiple continue preambles.

Browse source 
For feature parity with initial preambles.
Previously, continue preambles were for GFX6 only, but this is
about to change in the next commits.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22354>
This commit is contained in:
Timur Kristóf 2023-04-04 01:34:36 +02:00 • committed by Marge Bot
parent 8cea452bda
commit 6844506c3d
3 changed files with 33 additions and 24 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

34
src/amd/vulkan/radv_queue.c
View file

@ -1652,22 +1652,25 @@ radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submi
* before starting the next cmdbuffer, so we need to do it here.
*/
const bool need_wait = wait_count > 0;
unsigned num_preambles = 0;
struct radeon_cmdbuf *preambles[4] = {0};
unsigned num_initial_preambles = 0;
unsigned num_continue_preambles = 0;
struct radeon_cmdbuf *initial_preambles[4] = {0};
struct radeon_cmdbuf *continue_preambles[4] = {0};
if (queue->state.qf == RADV_QUEUE_GENERAL || queue->state.qf == RADV_QUEUE_COMPUTE) {
preambles[num_preambles++] =
initial_preambles[num_initial_preambles++] =
need_wait ? queue->state.initial_full_flush_preamble_cs : queue->state.initial_preamble_cs;
continue_preambles[num_continue_preambles++] = queue->state.continue_preamble_cs;
}
const unsigned num_1q_preambles = num_preambles;
const unsigned num_1q_initial_preambles = num_initial_preambles;
if (use_ace) {
preambles[num_preambles++] = queue->state.gang_wait_preamble_cs;
preambles[num_preambles++] = queue->ace_internal_state->gang_wait_preamble_cs;
preambles[num_preambles++] = need_wait
? queue->ace_internal_state->initial_full_flush_preamble_cs
: queue->ace_internal_state->initial_preamble_cs;
initial_preambles[num_initial_preambles++] = queue->state.gang_wait_preamble_cs;
initial_preambles[num_initial_preambles++] = queue->ace_internal_state->gang_wait_preamble_cs;
initial_preambles[num_initial_preambles++] =
need_wait ? queue->ace_internal_state->initial_full_flush_preamble_cs
: queue->ace_internal_state->initial_preamble_cs;
}
struct radv_winsys_submit_info submit = {
@ -1675,9 +1678,10 @@ radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submi
.queue_index = queue->vk.index_in_family,
.cs_array = cs_array,
.cs_count = 0,
.preamble_count = 1,
.initial_preamble_cs = preambles,
.continue_preamble_cs = queue->state.continue_preamble_cs,
.initial_preamble_count = 1,
.continue_preamble_count = 1,
.initial_preamble_cs = initial_preambles,
.continue_preamble_cs = continue_preambles,
.uses_shadow_regs = queue->state.uses_shadow_regs,
};
@ -1740,7 +1744,7 @@ radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submi
cs_array[num_submitted_cs++] = perf_ctr_unlock_cs;
submit.cs_count = num_submitted_cs;
submit.preamble_count = submit_ace ? num_preambles : num_1q_preambles;
submit.initial_preamble_count = submit_ace ? num_initial_preambles : num_1q_initial_preambles;
result = queue->device->ws->cs_submit(ctx, &submit, j == 0 ? wait_count : 0, waits,
last_submit ? submission->signal_count : 0,
@ -1757,8 +1761,8 @@ radv_queue_submit_normal(struct radv_queue *queue, struct vk_queue_submit *submi
radv_check_trap_handler(queue);
}
preambles[0] = queue->state.initial_preamble_cs;
preambles[1] = !use_ace ? NULL : queue->ace_internal_state->initial_preamble_cs;
initial_preambles[0] = queue->state.initial_preamble_cs;
initial_preambles[1] = !use_ace ? NULL : queue->ace_internal_state->initial_preamble_cs;
}
queue->last_shader_upload_seq =

5
src/amd/vulkan/radv_radeon_winsys.h
View file

@ -201,10 +201,11 @@ struct radv_winsys_submit_info {
enum amd_ip_type ip_type;
int queue_index;
unsigned cs_count;
unsigned preamble_count;
unsigned initial_preamble_count;
unsigned continue_preamble_count;
struct radeon_cmdbuf **cs_array;
struct radeon_cmdbuf **initial_preamble_cs;
struct radeon_cmdbuf *continue_preamble_cs;
struct radeon_cmdbuf **continue_preamble_cs;
bool uses_shadow_regs;
};

18
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View file

@ -1033,7 +1033,7 @@ static VkResult
radv_amdgpu_winsys_cs_submit_sysmem(struct radv_amdgpu_ctx *ctx, int queue_idx,
struct radv_winsys_sem_info *sem_info,
struct radeon_cmdbuf **cs_array, unsigned cs_count,
struct radeon_cmdbuf **initial_preamble_cs,
struct radeon_cmdbuf *initial_preamble_cs,
struct radeon_cmdbuf *continue_preamble_cs,
bool uses_shadow_regs)
{
@ -1052,8 +1052,7 @@ radv_amdgpu_winsys_cs_submit_sysmem(struct radv_amdgpu_ctx *ctx, int queue_idx,
for (unsigned i = 0; i < cs_count;) {
struct radv_amdgpu_cs_ib_info *ibs;
struct radeon_winsys_bo **bos;
struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs :
initial_preamble_cs ? initial_preamble_cs[0] : NULL;
struct radeon_cmdbuf *preamble_cs = i ? continue_preamble_cs : initial_preamble_cs;
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(cs_array[i]);
struct drm_amdgpu_bo_list_entry *handles = NULL;
unsigned num_handles = 0;
@ -1323,14 +1322,19 @@ radv_amdgpu_winsys_cs_submit_internal(struct radv_amdgpu_ctx *ctx,
if (!submit->cs_count) {
result = radv_amdgpu_cs_submit_zero(ctx, submit->ip_type, submit->queue_index, sem_info);
} else if (!ring_can_use_ib_bos(ctx->ws, submit->ip_type)) {
assert(submit->preamble_count <= 1);
assert(submit->initial_preamble_count <= 1);
assert(submit->continue_preamble_count <= 1);
struct radeon_cmdbuf *initial_preamble =
submit->initial_preamble_cs ? submit->initial_preamble_cs[0] : NULL;
struct radeon_cmdbuf *continue_preamble =
submit->continue_preamble_cs ? submit->continue_preamble_cs[0] : NULL;
result = radv_amdgpu_winsys_cs_submit_sysmem(
ctx, submit->queue_index, sem_info, submit->cs_array, submit->cs_count,
submit->initial_preamble_cs, submit->continue_preamble_cs, submit->uses_shadow_regs);
ctx, submit->queue_index, sem_info, submit->cs_array, submit->cs_count, initial_preamble,
continue_preamble, submit->uses_shadow_regs);
} else {
result = radv_amdgpu_winsys_cs_submit_fallback(
ctx, submit->queue_index, sem_info, submit->cs_array, submit->cs_count,
submit->initial_preamble_cs, submit->preamble_count, submit->uses_shadow_regs);
submit->initial_preamble_cs, submit->initial_preamble_count, submit->uses_shadow_regs);
}
return result;