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winsys/amdgpu: remove amdgpu_bo_sparse::gpu_address, use amdgpu_va_get_start_addr
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26914>
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parent
d05e029ff0
commit
68418db212
2 changed files with 10 additions and 8 deletions
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@ -1003,7 +1003,7 @@ static void amdgpu_bo_sparse_destroy(struct radeon_winsys *rws, struct pb_buffer
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r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0,
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(uint64_t)bo->num_va_pages * RADEON_SPARSE_PAGE_SIZE,
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bo->gpu_address, 0, AMDGPU_VA_OP_CLEAR);
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amdgpu_va_get_start_addr(bo->va_handle), 0, AMDGPU_VA_OP_CLEAR);
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if (r) {
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fprintf(stderr, "amdgpu: clearing PRT VA region on destroy failed (%d)\n", r);
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}
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@ -1060,14 +1060,15 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *ws, uint64_t size,
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/* For simplicity, we always map a multiple of the page size. */
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map_size = align64(size, RADEON_SPARSE_PAGE_SIZE);
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va_gap_size = ws->check_vm ? 4 * RADEON_SPARSE_PAGE_SIZE : 0;
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uint64_t gpu_address;
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r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
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map_size + va_gap_size, RADEON_SPARSE_PAGE_SIZE,
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0, &bo->gpu_address, &bo->va_handle,
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AMDGPU_VA_RANGE_HIGH);
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0, &gpu_address, &bo->va_handle, AMDGPU_VA_RANGE_HIGH);
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if (r)
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goto error_va_alloc;
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r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0, map_size, bo->gpu_address,
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r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0, map_size, gpu_address,
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AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
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if (r)
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goto error_va_map;
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@ -1140,7 +1141,8 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf,
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r = amdgpu_bo_va_op_raw(ws->dev, backing->bo->bo_handle,
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(uint64_t)backing_start * RADEON_SPARSE_PAGE_SIZE,
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(uint64_t)backing_size * RADEON_SPARSE_PAGE_SIZE,
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bo->gpu_address + (uint64_t)span_va_page * RADEON_SPARSE_PAGE_SIZE,
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amdgpu_va_get_start_addr(bo->va_handle) +
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(uint64_t)span_va_page * RADEON_SPARSE_PAGE_SIZE,
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AMDGPU_VM_PAGE_READABLE |
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AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_EXECUTABLE,
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@ -1165,7 +1167,8 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf,
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} else {
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r = amdgpu_bo_va_op_raw(ws->dev, NULL, 0,
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(uint64_t)(end_va_page - va_page) * RADEON_SPARSE_PAGE_SIZE,
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bo->gpu_address + (uint64_t)va_page * RADEON_SPARSE_PAGE_SIZE,
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amdgpu_va_get_start_addr(bo->va_handle) +
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(uint64_t)va_page * RADEON_SPARSE_PAGE_SIZE,
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AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_REPLACE);
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if (r) {
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ok = false;
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@ -1746,7 +1749,7 @@ uint64_t amdgpu_bo_get_va(struct pb_buffer_lean *buf)
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return amdgpu_va_get_start_addr(slab_bo->b.b.va_handle) + get_slab_entry_offset(bo);
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} else if (bo->type == AMDGPU_BO_SPARSE) {
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return get_sparse_bo(bo)->gpu_address;
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return amdgpu_va_get_start_addr(get_sparse_bo(bo)->va_handle);
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} else {
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return amdgpu_va_get_start_addr(get_real_bo(bo)->va_handle);
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}
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@ -103,7 +103,6 @@ struct amdgpu_bo_real_reusable {
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struct amdgpu_bo_sparse {
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struct amdgpu_winsys_bo b;
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amdgpu_va_handle va_handle;
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uint64_t gpu_address;
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uint32_t num_va_pages;
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uint32_t num_backing_pages;
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