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treewide: use nir_break_if

Browse source 
Via Coccinelle patch:

    @@
    expression builder, condition;
    @@

    -nir_push_if(builder, condition);
    -{
    -nir_jump(builder, nir_jump_break);
    -}
    -nir_pop_if(builder, NULL);
    +nir_break_if(builder, condition);

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35794>
This commit is contained in:
Alyssa Rosenzweig 2025-06-27 10:57:37 -04:00
parent 9c47461889
commit 67237b6f1b
9 changed files with 12 additions and 50 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/amd/compiler/instruction_selection/aco_isel_setup.cpp
View file

@ -136,9 +136,7 @@ sanitize_cf_list(nir_function_impl* impl, struct exec_list* cf_list)
/* We don't use block divergence information, so just this is enough. */
cond->divergent = false;
nir_push_if(&b, cond);
nir_jump(&b, nir_jump_break);
nir_pop_if(&b, NULL);
nir_break_if(&b, cond);
progress = true;
}

6
src/amd/vulkan/radv_query.c
View file

@ -251,11 +251,7 @@ build_occlusion_query_shader(struct radv_device *device)
nir_def *load = nir_build_load_global(&b, 1, 32, nir_iadd(&b, src_va, nir_u2u64(&b, load_offset)),
.align_mul = 4, .access = ACCESS_COHERENT);
nir_push_if(&b, nir_ige_imm(&b, load, 0x80000000));
{
nir_jump(&b, nir_jump_break);
}
nir_pop_if(&b, NULL);
nir_break_if(&b, nir_ige_imm(&b, load, 0x80000000));
}
nir_pop_loop(&b, NULL);
}

6
src/asahi/lib/agx_nir_lower_gs.c
View file

@ -1003,11 +1003,7 @@ agx_nir_lower_gs_instancing(nir_shader *gs)
nir_loop *loop = nir_push_loop(&b);
{
index = nir_load_var(&b, i);
nir_push_if(&b, nir_uge_imm(&b, index, nr_invocations));
{
nir_jump(&b, nir_jump_break);
}
nir_pop_if(&b, NULL);
nir_break_if(&b, nir_uge_imm(&b, index, nr_invocations));
b.cursor = nir_cf_reinsert(&list, b.cursor);
nir_store_var(&b, i, nir_iadd_imm(&b, index, 1), ~0);

6
src/asahi/lib/agx_nir_lower_msaa.c
View file

@ -94,11 +94,7 @@ agx_nir_wrap_per_sample_loop(nir_shader *shader, uint8_t nr_samples)
nir_loop *loop = nir_push_loop(&b);
{
bit = nir_load_var(&b, i);
nir_push_if(&b, nir_uge(&b, bit, end_bit));
{
nir_jump(&b, nir_jump_break);
}
nir_pop_if(&b, NULL);
nir_break_if(&b, nir_uge(&b, bit, end_bit));
b.cursor = nir_cf_reinsert(&list, b.cursor);
nir_store_var(&b, i, nir_ishl_imm(&b, bit, 1), ~0);

6
src/compiler/nir/nir_lower_memcpy.c
View file

@ -159,11 +159,7 @@ lower_memcpy_impl(nir_function_impl *impl)
nir_push_loop(&b);
{
nir_def *index = nir_load_var(&b, i);
nir_push_if(&b, nir_uge(&b, index, size));
{
nir_jump(&b, nir_jump_break);
}
nir_pop_if(&b, NULL);
nir_break_if(&b, nir_uge(&b, index, size));
nir_def *value =
memcpy_load_deref_elem(&b, copy_src, index);

12
src/compiler/nir/nir_lower_variable_initializers.c
View file

@ -177,11 +177,7 @@ nir_zero_initialize_shared_memory(nir_shader *shader,
{
nir_def *offset = nir_load_var(&b, it);
nir_push_if(&b, nir_uge_imm(&b, offset, shared_size));
{
nir_jump(&b, nir_jump_break);
}
nir_pop_if(&b, NULL);
nir_break_if(&b, nir_uge_imm(&b, offset, shared_size));
nir_store_shared(&b, nir_imm_zero(&b, chunk_comps, 32), offset,
.align_mul = chunk_size,
@ -270,11 +266,7 @@ nir_clear_shared_memory(nir_shader *shader,
{
nir_def *offset = &offset_phi->def;
nir_push_if(&b, nir_uge_imm(&b, offset, shared_size));
{
nir_jump(&b, nir_jump_break);
}
nir_pop_if(&b, NULL);
nir_break_if(&b, nir_uge_imm(&b, offset, shared_size));
nir_store_shared(&b, value, offset,
.align_mul = chunk_size,
.write_mask = ((1 << chunk_comps) - 1));

4
src/gallium/drivers/zink/zink_compiler.c
View file

@ -707,9 +707,7 @@ lower_line_stipple_fs(nir_shader *shader)
nir_def *index_mask = nir_ishl(&b, nir_imm_int(&b, 1), index);
nir_def *new_value = nir_ixor(&b, value, index_mask);
nir_store_var(&b, v, new_value, 1);
nir_push_if(&b, nir_ieq_imm(&b, value, 0));
nir_jump(&b, nir_jump_break);
nir_pop_if(&b, NULL);
nir_break_if(&b, nir_ieq_imm(&b, value, 0));
nir_def *stipple_pos =
nir_interp_deref_at_sample(&b, 1, 32,

4
src/microsoft/vulkan/dzn_nir.c
View file

@ -384,9 +384,7 @@ dzn_nir_triangle_fan_prim_restart_rewrite_index_shader(uint8_t old_index_size)
nir_def *read_index_count =
nir_bcsel(&b, nir_ieq(&b, index0, prim_restart_val),
nir_imm_int(&b, 3), nir_imm_int(&b, 2));
nir_push_if(&b, nir_ult(&b, old_index_count, nir_iadd(&b, old_index_ptr, read_index_count)));
nir_jump(&b, nir_jump_break);
nir_pop_if(&b, NULL);
nir_break_if(&b, nir_ult(&b, old_index_count, nir_iadd(&b, old_index_ptr, read_index_count)));
nir_def *old_index_offset =
nir_imul_imm(&b, old_index_ptr, old_index_size);

14
src/nouveau/vulkan/nvk_cmd_indirect.c
View file

@ -181,11 +181,7 @@ nvk_nir_push_copy_dws(nir_builder *b, struct nvk_nir_push *p,
nir_push_loop(b);
{
nir_push_if(b, nir_uge(b, nir_load_var(b, i), dw_count));
{
nir_jump(b, nir_jump_break);
}
nir_pop_if(b, NULL);
nir_break_if(b, nir_uge(b, nir_load_var(b, i), dw_count));
nir_def *dw = load_global_dw(b, nir_load_var(b, src_dw_addr), 0);
store_global_dw(b, nir_load_var(b, p->addr), 0, dw);
@ -215,12 +211,8 @@ nvk_nir_build_pad_NOP(nir_builder *b, struct nvk_nir_push *p, uint32_t nop)
{
nir_push_loop(b);
{
nir_push_if(b, nir_uge_imm(b, nir_load_var(b, p->dw_count),
p->max_dw_count));
{
nir_jump(b, nir_jump_break);
}
nir_pop_if(b, NULL);
nir_break_if(b, nir_uge_imm(b, nir_load_var(b, p->dw_count),
p->max_dw_count));
store_global_dw(b, nir_load_var(b, p->addr), 0, nir_imm_int(b, nop));
nir_iadd_to_var_imm(b, p->addr, 4);